Intrinsic<[], [llvm_i32_ty], []> {
}
+def int_amdgcn_s_incperflevel :
+ GCCBuiltin<"__builtin_amdgcn_s_incperflevel">,
+ Intrinsic<[], [llvm_i32_ty], []> {
+}
+
+def int_amdgcn_s_decperflevel :
+ GCCBuiltin<"__builtin_amdgcn_s_decperflevel">,
+ Intrinsic<[], [llvm_i32_ty], []> {
+}
+
def int_amdgcn_s_getreg :
GCCBuiltin<"__builtin_amdgcn_s_getreg">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrReadMem]>;
def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> {
let simm16 = 0;
}
-def S_INCPERFLEVEL : SOPP <0x00000014, (ins i16imm:$simm16), "s_incperflevel $simm16">;
-def S_DECPERFLEVEL : SOPP <0x00000015, (ins i16imm:$simm16), "s_decperflevel $simm16">;
+def S_INCPERFLEVEL : SOPP <0x00000014, (ins i32imm:$simm16), "s_incperflevel $simm16",
+ [(int_amdgcn_s_incperflevel SIMM16bit:$simm16)]> {
+ let hasSideEffects = 1;
+ let mayLoad = 1;
+ let mayStore = 1;
+}
+def S_DECPERFLEVEL : SOPP <0x00000015, (ins i32imm:$simm16), "s_decperflevel $simm16",
+ [(int_amdgcn_s_decperflevel SIMM16bit:$simm16)]> {
+ let hasSideEffects = 1;
+ let mayLoad = 1;
+ let mayStore = 1;
+}
def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> {
let simm16 = 0;
}
--- /dev/null
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+declare void @llvm.amdgcn.s.decperflevel(i32) #0
+
+; GCN-LABEL: {{^}}test_s_decperflevel:
+; GCN: s_decperflevel 0{{$}}
+; GCN: s_decperflevel 1{{$}}
+; GCN: s_decperflevel 2{{$}}
+; GCN: s_decperflevel 3{{$}}
+; GCN: s_decperflevel 4{{$}}
+; GCN: s_decperflevel 5{{$}}
+; GCN: s_decperflevel 6{{$}}
+; GCN: s_decperflevel 7{{$}}
+; GCN: s_decperflevel 8{{$}}
+; GCN: s_decperflevel 9{{$}}
+; GCN: s_decperflevel 10{{$}}
+; GCN: s_decperflevel 11{{$}}
+; GCN: s_decperflevel 12{{$}}
+; GCN: s_decperflevel 13{{$}}
+; GCN: s_decperflevel 14{{$}}
+; GCN: s_decperflevel 15{{$}}
+define void @test_s_decperflevel(i32 %x) #0 {
+ call void @llvm.amdgcn.s.decperflevel(i32 0)
+ call void @llvm.amdgcn.s.decperflevel(i32 1)
+ call void @llvm.amdgcn.s.decperflevel(i32 2)
+ call void @llvm.amdgcn.s.decperflevel(i32 3)
+ call void @llvm.amdgcn.s.decperflevel(i32 4)
+ call void @llvm.amdgcn.s.decperflevel(i32 5)
+ call void @llvm.amdgcn.s.decperflevel(i32 6)
+ call void @llvm.amdgcn.s.decperflevel(i32 7)
+ call void @llvm.amdgcn.s.decperflevel(i32 8)
+ call void @llvm.amdgcn.s.decperflevel(i32 9)
+ call void @llvm.amdgcn.s.decperflevel(i32 10)
+ call void @llvm.amdgcn.s.decperflevel(i32 11)
+ call void @llvm.amdgcn.s.decperflevel(i32 12)
+ call void @llvm.amdgcn.s.decperflevel(i32 13)
+ call void @llvm.amdgcn.s.decperflevel(i32 14)
+ call void @llvm.amdgcn.s.decperflevel(i32 15)
+ ret void
+}
+
+attributes #0 = { nounwind }
--- /dev/null
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+declare void @llvm.amdgcn.s.incperflevel(i32) #0
+
+; GCN-LABEL: {{^}}test_s_incperflevel:
+; GCN: s_incperflevel 0{{$}}
+; GCN: s_incperflevel 1{{$}}
+; GCN: s_incperflevel 2{{$}}
+; GCN: s_incperflevel 3{{$}}
+; GCN: s_incperflevel 4{{$}}
+; GCN: s_incperflevel 5{{$}}
+; GCN: s_incperflevel 6{{$}}
+; GCN: s_incperflevel 7{{$}}
+; GCN: s_incperflevel 8{{$}}
+; GCN: s_incperflevel 9{{$}}
+; GCN: s_incperflevel 10{{$}}
+; GCN: s_incperflevel 11{{$}}
+; GCN: s_incperflevel 12{{$}}
+; GCN: s_incperflevel 13{{$}}
+; GCN: s_incperflevel 14{{$}}
+; GCN: s_incperflevel 15{{$}}
+define void @test_s_incperflevel(i32 %x) #0 {
+ call void @llvm.amdgcn.s.incperflevel(i32 0)
+ call void @llvm.amdgcn.s.incperflevel(i32 1)
+ call void @llvm.amdgcn.s.incperflevel(i32 2)
+ call void @llvm.amdgcn.s.incperflevel(i32 3)
+ call void @llvm.amdgcn.s.incperflevel(i32 4)
+ call void @llvm.amdgcn.s.incperflevel(i32 5)
+ call void @llvm.amdgcn.s.incperflevel(i32 6)
+ call void @llvm.amdgcn.s.incperflevel(i32 7)
+ call void @llvm.amdgcn.s.incperflevel(i32 8)
+ call void @llvm.amdgcn.s.incperflevel(i32 9)
+ call void @llvm.amdgcn.s.incperflevel(i32 10)
+ call void @llvm.amdgcn.s.incperflevel(i32 11)
+ call void @llvm.amdgcn.s.incperflevel(i32 12)
+ call void @llvm.amdgcn.s.incperflevel(i32 13)
+ call void @llvm.amdgcn.s.incperflevel(i32 14)
+ call void @llvm.amdgcn.s.incperflevel(i32 15)
+ ret void
+}
+
+attributes #0 = { nounwind }