soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl

This adds the necessary bits to drive the VPU blk-ctrl on the i.MX8MQ, to
avoid putting more of this functionality into the decoder driver.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 511e74f..122f9c8 100644 (file)
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -15,6 +15,7 @@
 
 #include <dt-bindings/power/imx8mm-power.h>
 #include <dt-bindings/power/imx8mn-power.h>
+#include <dt-bindings/power/imx8mq-power.h>
 
 #define BLK_SFT_RSTN   0x0
 #define BLK_CLK_EN     0x4
@@ -589,6 +590,68 @@ static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
        .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
 };
 
+static int imx8mq_vpu_power_notifier(struct notifier_block *nb,
+                                    unsigned long action, void *data)
+{
+       struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+                                                power_nb);
+
+       if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+               return NOTIFY_OK;
+
+       /*
+        * The ADB in the VPUMIX domain has no separate reset and clock
+        * enable bits, but is ungated and reset together with the VPUs. The
+        * reset and clock enable inputs to the ADB is a logical OR of the
+        * VPU bits. In order to set the G2 fuse bits, the G2 clock must
+        * also be enabled.
+        */
+       regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1));
+       regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1));
+
+       if (action == GENPD_NOTIFY_ON) {
+               /*
+                * On power up we have no software backchannel to the GPC to
+                * wait for the ADB handshake to happen, so we just delay for a
+                * bit. On power down the GPC driver waits for the handshake.
+                */
+               udelay(5);
+
+               /* set "fuse" bits to enable the VPUs */
+               regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
+               regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
+               regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
+       }
+
+       return NOTIFY_OK;
+}
+
+static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = {
+       [IMX8MQ_VPUBLK_PD_G1] = {
+               .name = "vpublk-g1",
+               .clk_names = (const char *[]){ "g1", },
+               .num_clks = 1,
+               .gpc_name = "g1",
+               .rst_mask = BIT(1),
+               .clk_mask = BIT(1),
+       },
+       [IMX8MQ_VPUBLK_PD_G2] = {
+               .name = "vpublk-g2",
+               .clk_names = (const char *[]){ "g2", },
+               .num_clks = 1,
+               .gpc_name = "g2",
+               .rst_mask = BIT(0),
+               .clk_mask = BIT(0),
+       },
+};
+
+static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = {
+       .max_reg = 0x14,
+       .power_notifier_fn = imx8mq_vpu_power_notifier,
+       .domains = imx8mq_vpu_blk_ctl_domain_data,
+       .num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data),
+};
+
 static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
        {
                .compatible = "fsl,imx8mm-vpu-blk-ctrl",
@@ -600,6 +663,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
                .compatible = "fsl,imx8mn-disp-blk-ctrl",
                .data = &imx8mn_disp_blk_ctl_dev_data
        }, {
+               .compatible = "fsl,imx8mq-vpu-blk-ctrl",
+               .data = &imx8mq_vpu_blk_ctl_dev_data
+       }, {
                /* Sentinel */
        }
 };