s5pc110: gpio: added gpio interfaces and definitions for drive strength.

Signed-off-by: daeinki <inki.dae@samsung.com>

diff --git a/cpu/arm_cortexa8/s5pc1xx/gpio.c b/cpu/arm_cortexa8/s5pc1xx/gpio.c
index befcf8d..bbec25a 100644 (file)
--- a/cpu/arm_cortexa8/s5pc1xx/gpio.c
+++ b/cpu/arm_cortexa8/s5pc1xx/gpio.c
@@ -31,6 +31,11 @@
 #define PULL_MASK(x)           (0x3 << ((x) << 1))
 #define PULL_MODE(x, v)                ((v) << ((x) << 1))
 
+#define DRV_MASK(x)            (0x3 << (x))
+#define DRV_SET(x,m)           ((m) << (x))
+#define RATE_MASK(x)           (0x1 << (x + 16))
+#define RATE_SET(x)            (0x1 << (x + 16))
+
 void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg)
 {
        unsigned int value;
@@ -94,3 +99,43 @@ void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
        }
        writel(value, &bank->pull);
 }
+
+void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+       unsigned int value;
+
+       value = readl(&bank->drv);
+       value &= ~DRV_MASK(gpio);
+
+       switch (mode) {
+       case GPIO_DRV_1x:
+       case GPIO_DRV_2x:
+       case GPIO_DRV_3x:
+       case GPIO_DRV_4x:
+               value |= DRV_SET(gpio, mode);
+               break;
+       default:
+               break;
+       }
+
+       writel(value, &bank->drv);
+}
+
+void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+       unsigned int value;
+
+       value = readl(&bank->drv);
+       value &= ~RATE_MASK(gpio);
+
+       switch (mode) {
+       case GPIO_DRV_FAST:
+       case GPIO_DRV_SLOW:
+               value |= RATE_SET(gpio);
+               break;
+       default:
+               break;
+       }
+
+       writel(value, &bank->drv);
+}

diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h
index 9dea290..ea7311f 100644 (file)
--- a/include/asm-arm/arch-s5pc1xx/gpio.h
+++ b/include/asm-arm/arch-s5pc1xx/gpio.h
@@ -132,16 +132,27 @@ void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio);
 void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int enable);
 unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio);
 void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
+void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
+void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
 #endif
 
 /* Pin configurations */
 #define GPIO_INPUT     0x0
 #define GPIO_OUTPUT    0x1
 #define GPIO_IRQ       0xf
+#define GPIO_FUNC(x)   (x)
 
 /* Pull mode */
 #define GPIO_PULL_NONE 0x0
 #define GPIO_PULL_DOWN 0x1
 #define GPIO_PULL_UP   0x2
 
+/* Drive Strength level */
+#define GPIO_DRV_1x    0x0
+#define GPIO_DRV_2x    0x1
+#define GPIO_DRV_3x    0x2
+#define GPIO_DRV_4x    0x3
+#define GPIO_DRV_FAST  0x0
+#define GPIO_DRV_SLOW  0x1
+
 #endif