{
struct davinci_gpio_controller *d = chip2controller(chip);
- return irq_create_mapping(d->irq_domain, d->chip.base + offset);
+ if (d->irq_domain)
+ return irq_create_mapping(d->irq_domain, d->chip.base + offset);
+ else
+ return -ENXIO;
}
static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
struct davinci_gpio_platform_data *pdata = dev->platform_data;
struct davinci_gpio_regs __iomem *g;
- struct irq_domain *irq_domain;
+ struct irq_domain *irq_domain = NULL;
ngpio = pdata->ngpio;
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
}
clk_prepare_enable(clk);
- irq = irq_alloc_descs(-1, 0, ngpio, 0);
- if (irq < 0) {
- dev_err(dev, "Couldn't allocate IRQ numbers\n");
- return irq;
- }
+ if (!pdata->gpio_unbanked) {
+ irq = irq_alloc_descs(-1, 0, ngpio, 0);
+ if (irq < 0) {
+ dev_err(dev, "Couldn't allocate IRQ numbers\n");
+ return irq;
+ }
- irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0,
- &davinci_gpio_irq_ops,
- chips);
- if (!irq_domain) {
- dev_err(dev, "Couldn't register an IRQ domain\n");
- return -ENODEV;
+ irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0,
+ &davinci_gpio_irq_ops,
+ chips);
+ if (!irq_domain) {
+ dev_err(dev, "Couldn't register an IRQ domain\n");
+ return -ENODEV;
+ }
}
/*
*/
for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
chips[bank].chip.to_irq = gpio_to_irq_banked;
- if (!pdata->gpio_unbanked)
- chips[bank].irq_domain = irq_domain;
+ chips[bank].irq_domain = irq_domain;
}
/*