drm/amd/display: add hdmi2.1 dsc pps packet programming

This change adds EMP packet programming for enabling dsc with
hdmi. The packets are structured according to VESA HDMI 2.1x
r2 spec, section 10.10.2.2.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index caa7075..07533cc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2771,10 +2771,10 @@ void core_link_enable_stream(
                        allocate_mst_payload(pipe_ctx);
 
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-               if (pipe_ctx->stream->timing.flags.DSC &&
-                               (dc_is_dp_signal(pipe_ctx->stream->signal) ||
-                               dc_is_virtual_signal(pipe_ctx->stream->signal))) {
-                       dp_set_dsc_enable(pipe_ctx, true);
+               if (pipe_ctx->stream->timing.flags.DSC) {
+                       if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+                                       dc_is_virtual_signal(pipe_ctx->stream->signal))
+                               dp_set_dsc_enable(pipe_ctx, true);
                        pipe_ctx->stream_res.tg->funcs->wait_for_state(
                                        pipe_ctx->stream_res.tg,
                                        CRTC_STATE_VBLANK);
@@ -2835,9 +2835,9 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
 
        disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-       if (pipe_ctx->stream->timing.flags.DSC &&
-                       dc_is_dp_signal(pipe_ctx->stream->signal)) {
-               dp_set_dsc_enable(pipe_ctx, false);
+       if (pipe_ctx->stream->timing.flags.DSC) {
+               if (dc_is_dp_signal(pipe_ctx->stream->signal))
+                       dp_set_dsc_enable(pipe_ctx, false);
        }
 #endif
 }

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 211fade..46257f0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -396,7 +396,7 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
 
 /* This has to be done after DSC was enabled on RX first, i.e. after dp_enable_dsc_on_rx() had been called
  */
-static void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+void set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
 {
        struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
        struct dc *core_dc = pipe_ctx->stream->ctx->dc;
@@ -435,7 +435,7 @@ static void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
 
                dsc_optc_config_log(dsc, &dsc_optc_cfg);
                /* Enable DSC in encoder */
-               if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) && pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config)
+               if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
                        pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
                                                                        optc_dsc_mode,
                                                                        dsc_optc_cfg.bytes_per_pixel,
@@ -454,11 +454,10 @@ static void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
                                OPTC_DSC_DISABLED, 0, 0);
 
                /* disable DSC in stream encoder */
-               if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
+               if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
                        pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
                                        pipe_ctx->stream_res.stream_enc,
                                        OPTC_DSC_DISABLED, 0, 0, NULL);
-               }
 
                /* disable DSC block */
                pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
@@ -479,12 +478,12 @@ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
 
        if (enable) {
                if (dp_set_dsc_on_rx(pipe_ctx, true)) {
-                       dp_set_dsc_on_stream(pipe_ctx, true);
+                       set_dsc_on_stream(pipe_ctx, true);
                        result = true;
                }
        } else {
                dp_set_dsc_on_rx(pipe_ctx, false);
-               dp_set_dsc_on_stream(pipe_ctx, false);
+               set_dsc_on_stream(pipe_ctx, false);
                result = true;
        }
 out:
@@ -500,7 +499,7 @@ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx)
        if (!dsc)
                return false;
 
-       dp_set_dsc_on_stream(pipe_ctx, true);
+       set_dsc_on_stream(pipe_ctx, true);
        return true;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 5fc4e09..ddf15a3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1783,8 +1783,9 @@ static void dcn20_reset_back_end_for_pipe(
                }
        }
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-       else if (pipe_ctx->stream_res.dsc)
+       else if (pipe_ctx->stream_res.dsc) {
                dp_set_dsc_enable(pipe_ctx, false);
+       }
 #endif
 
        /* by upper caller loop, parent pipe: pipe0, will be reset last.

diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index 2d95eff..c5293f9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -66,6 +66,7 @@ void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
 void dp_set_fec_ready(struct dc_link *link, bool ready);
 void dp_set_fec_enable(struct dc_link *link, bool enable);
 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
+void set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
 #endif