83xx, kmeter1: updates for 2009.03

- HRCW update
  HRCWH_BOOTSEQ_DISABLE not HRCWH_BOOTSEQ_NORMAL
  HRCWH_LALE_EARLY added
- DDR-SDRAM settings modified. This solves sporadically
  problems with this memory.
- CS1 now 128 MB window size
- CS3 now 512 MB window size
- PRAM activated
- MTDPARTS_DEFAULT defined
- CONFIG_HOSTNAME added
- MONITOR_LEN now 384 KB

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index ef3faa5..49a801f 100644 (file)
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -28,6 +28,7 @@
 #define CONFIG_MPC83XX         1 /* MPC83XX family */
 #define CONFIG_MPC8360         1 /* MPC8360 CPU specific */
 #define CONFIG_KMETER1         1 /* KMETER1 board specific */
+#define CONFIG_HOSTNAME                kmeter1
 
 /* include common defines/options for all Keymile boards */
 #include "keymile-common.h"
@@ -52,10 +53,11 @@
 #define CONFIG_SYS_HRCW_HIGH (\
        HRCWH_CORE_ENABLE | \
        HRCWH_FROM_0X00000100 | \
-       HRCWH_BOOTSEQ_NORMAL | \
+       HRCWH_BOOTSEQ_DISABLE | \
        HRCWH_SW_WATCHDOG_DISABLE | \
        HRCWH_ROM_LOC_LOCAL_16BIT | \
        HRCWH_BIG_ENDIAN | \
+       HRCWH_LALE_EARLY | \
        HRCWH_LDP_CLEAR )
 
 /*
@@ -102,11 +104,12 @@
                                         SDRAM_CFG_SREN)
 #define CONFIG_SYS_DDR_SDRAM_CFG2      0x00401000
 #define CONFIG_SYS_DDR_CLK_CNTL        (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL        ((0x100 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
-                                (0x406 << SDRAM_INTERVAL_REFINT_SHIFT))
+#define CONFIG_SYS_DDR_INTERVAL        ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+                                (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
 
-#define CONFIG_SYS_DDR_MODE            0x04440242
-#define CONFIG_SYS_DDR_MODE2           0x00800000
+#define        CONFIG_SYS_DDRCDR               0x40000001
+#define CONFIG_SYS_DDR_MODE            0x47860452
+#define CONFIG_SYS_DDR_MODE2           0x8080c000
 
 #define CONFIG_SYS_DDR_TIMING_0        ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
                                 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
@@ -117,22 +120,22 @@
                                 (0 << TIMING_CFG0_WRT_SHIFT) | \
                                 (0 << TIMING_CFG0_RWT_SHIFT))
 
-#define CONFIG_SYS_DDR_TIMING_1        ((      TIMING_CFG1_CASLAT_40) | \
+#define CONFIG_SYS_DDR_TIMING_1        ((      TIMING_CFG1_CASLAT_50) | \
                                 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
-                                ( 1 << TIMING_CFG1_ACTTOACT_SHIFT) | \
-                                ( 2 << TIMING_CFG1_WRREC_SHIFT) | \
-                                ( 2 << TIMING_CFG1_REFREC_SHIFT) | \
-                                ( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \
-                                ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
-                                ( 2 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2        ((5 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+                                ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+                                ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
+                                ( 7 << TIMING_CFG1_REFREC_SHIFT) | \
+                                ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+                                ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+                                ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2        ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
                                 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
                                 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
-                                (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
-                                (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+                                (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+                                (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
                                 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
-                                (4 << TIMING_CFG2_CPO_SHIFT))
+                                (5 << TIMING_CFG2_CPO_SHIFT))
 
 #define CONFIG_SYS_DDR_TIMING_3        0x00000000
 
@@ -142,9 +145,10 @@
 #define CONFIG_SYS_MONITOR_BASE        TEXT_BASE /* start of monitor */
 #define CONFIG_SYS_FLASH_BASE          0xF0000000
 #define CONFIG_SYS_FLASH_BASE_1                0xF2000000
-#define CONFIG_SYS_PIGGY_BASE          0x80000000
+#define CONFIG_SYS_PIGGY_BASE          0xE8000000
+#define        CONFIG_SYS_PIGGY_SIZE           128
 #define CONFIG_SYS_PAXE_BASE           0xA0000000
-#define        CONFIG_SYS_PAXE_SIZE            256
+#define        CONFIG_SYS_PAXE_SIZE            512
 
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_RAMBOOT
@@ -152,7 +156,7 @@
 #undef CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN         (384 * 1024) /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN          (128 * 1024) /* Reserved for malloc */
 
 /*
@@ -175,8 +179,8 @@
  * Bank Bus     Machine PortSz  Size  Device
  * ---- ---     ------- ------  -----  ------
  *  0   Local   GPCM    16 bit  256MB FLASH
- *  1   Local   GPCM     8 bit  256KB GPIO/PIGGY
- *  3   Local   GPCM     8 bit  256MB PAXE
+ *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
+ *  3   Local   GPCM     8 bit  512MB PAXE
  *
  */
 /*
@@ -210,12 +214,12 @@
  * PRIO1/PIGGY on the local bus CS1
  */
 #define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
-#define CONFIG_SYS_LBLAWAR1_PRELIM     0x80000011 /* 256KB window size */
+#define CONFIG_SYS_LBLAWAR1_PRELIM     0x8000001A /* 128MB window size */
 
 #define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_PIGGY_BASE | \
                                (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
                                BR_V)
-#define CONFIG_SYS_OR1_PRELIM          (0xfffc0000 | /* 256KB */ \
+#define CONFIG_SYS_OR1_PRELIM          (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_2 | \
                                OR_GPCM_TRLX | OR_GPCM_EAD)
@@ -224,7 +228,7 @@
  * PAXE on the local bus CS3
  */
 #define CONFIG_SYS_LBLAWBAR3_PRELIM    CONFIG_SYS_PAXE_BASE /* Window base at flash base */
-#define CONFIG_SYS_LBLAWAR3_PRELIM     0x8000001b /* 256MB window size */
+#define CONFIG_SYS_LBLAWAR3_PRELIM     0x8000001C /* 512MB window size */
 
 #define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_PAXE_BASE | \
                                (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
@@ -297,7 +301,7 @@
 #else /* CFG_RAMBOOT */
 #define CONFIG_SYS_NO_FLASH            1       /* Flash is not usable now */
 #define CONFIG_ENV_IS_NOWHERE  1       /* Store ENV in memory only */
-#define CONFIG_ENV_ADDR                (CFG_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE                0x2000
 #endif /* CFG_RAMBOOT */
 
@@ -378,7 +382,7 @@
 
 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT2L      (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U      (CONFIG_SYS_PIGGY_BASE | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2U      (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT2L      (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT2U      CONFIG_SYS_IBAT2U
@@ -398,7 +402,7 @@
 
 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT5L      (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_PAXE_BASE | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT5L      (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT5U      CONFIG_SYS_IBAT5U
@@ -434,16 +438,25 @@
 #define BOOTFLAG_COLD  0x01 /* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM  0x02 /* Software reboot */
 
+#define BOOTFLASH_START        F0000000
+
+#define CONFIG_PRAM    512     /* protected RAM [KBytes] */
+
+#define MTDIDS_DEFAULT         "nor0=app"
+#define MTDPARTS_DEFAULT \
+       "mtdparts=app:256k(u-boot),128k(env),128k(envred),"     \
+       "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)"
+
 /*
  * Environment Configuration
  */
 #define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
+#ifndef CONFIG_KM_DEF_ENV              /* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
 #endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
+       CONFIG_KM_DEF_ENV                                               \
        "netdev=eth0\0"                                                 \
        "rootpath=/opt/eldk/ppc_82xx\0"                                 \
        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
@@ -487,6 +500,12 @@
        "unlock=yes\0"                                                  \
        "EEprom_ivm=pca9547:70:9\0"                                     \
        "dtt_bus=pca9547:70:a\0"                                        \
+       "mtdids=nor0=app \0"                                            \
+       "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"                       \
    ""
 
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#endif
+
 #endif /* __CONFIG_H */