}
bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
+ // If the ISel pipeline failed, do not bother running that pass.
+ if (MF.getProperties().hasProperty(
+ MachineFunctionProperties::Property::FailedISel))
+ return false;
+
DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
const InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
}
bool MachineLegalizePass::runOnMachineFunction(MachineFunction &MF) {
+ // If the ISel pipeline failed, do not bother running that pass.
+ if (MF.getProperties().hasProperty(
+ MachineFunctionProperties::Property::FailedISel))
+ return false;
DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n');
init(MF);
const MachineLegalizer &Legalizer = *MF.getSubtarget().getMachineLegalizer();
}
bool RegBankSelect::runOnMachineFunction(MachineFunction &MF) {
+ // If the ISel pipeline failed, do not bother running that pass.
+ if (MF.getProperties().hasProperty(
+ MachineFunctionProperties::Property::FailedISel))
+ return false;
+
DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n');
const Function *F = MF.getFunction();
Mode SaveOptMode = OptMode;