defm V_WRITELANE_B32 : VOP3_Real_gfx10<0x361>;
} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
+let SubtargetPredicate = isGFX10Before1030 in {
+ defm V_MUL_LO_I32 : VOP3_Real_gfx10<0x16b>;
+}
+
defm V_XOR3_B32 : VOP3_Real_gfx10<0x178>;
defm V_LSHLREV_B64 : VOP3_Real_gfx10<0x2ff>;
defm V_LSHRREV_B64 : VOP3_Real_gfx10<0x300>;
defm V_LSHL_B64 : VOP3_Real_gfx6_gfx7<0x161>;
defm V_LSHR_B64 : VOP3_Real_gfx6_gfx7<0x162>;
defm V_ASHR_I64 : VOP3_Real_gfx6_gfx7<0x163>;
+defm V_MUL_LO_I32 : VOP3_Real_gfx6_gfx7<0x16b>;
defm V_MAD_LEGACY_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x140>;
defm V_MAD_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x141>;
defm V_LDEXP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x168>;
defm V_MUL_LO_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x169>;
defm V_MUL_HI_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x16a>;
-defm V_MUL_LO_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16b>;
defm V_MUL_HI_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16c>;
defm V_DIV_FMAS_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x16f>;
defm V_DIV_FMAS_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x170>;
v_mul_hi_u32 v5, v1, -4.0
// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xef,0x01,0x00]
+v_mul_lo_i32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_lo_i32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x6b,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_lo_i32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0xff,0x05,0x02,0x00]
+
+v_mul_lo_i32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x01,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x67,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x77,0x04,0x02,0x00]
+
v_mul_hi_i32 v5, v1, v2
// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0x05,0x02,0x00]