ARM: dts: qcom: msm8974: add second DSI host and PHY

Add second DSI host and PHY available on the msm8974 platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221204124508.1415713-10-dmitry.baryshkov@linaro.org

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 8d216a3..7b8af64 100644 (file)
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1575,6 +1575,13 @@
                                                        remote-endpoint = <&dsi0_in>;
                                                };
                                        };
+
+                                       port@1 {
+                                               reg = <1>;
+                                               mdp5_intf2_out: endpoint {
+                                                       remote-endpoint = <&dsi1_in>;
+                                               };
+                                       };
                                };
                        };
 
@@ -1647,6 +1654,76 @@
 
                                status = "disabled";
                        };
+
+                       dsi1: dsi@fd922e00 {
+                               compatible = "qcom,mdss-dsi-ctrl";
+                               reg = <0xfd922e00 0x1f8>;
+                               reg-names = "dsi_ctrl";
+
+                               interrupt-parent = <&mdss>;
+                               interrupts = <4>;
+
+                               assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
+                               assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
+
+                               clocks = <&mmcc MDSS_MDP_CLK>,
+                                        <&mmcc MDSS_AHB_CLK>,
+                                        <&mmcc MDSS_AXI_CLK>,
+                                        <&mmcc MDSS_BYTE1_CLK>,
+                                        <&mmcc MDSS_PCLK1_CLK>,
+                                        <&mmcc MDSS_ESC1_CLK>,
+                                        <&mmcc MMSS_MISC_AHB_CLK>;
+                               clock-names = "mdp_core",
+                                             "iface",
+                                             "bus",
+                                             "byte",
+                                             "pixel",
+                                             "core",
+                                             "core_mmss";
+
+                               phys = <&dsi1_phy>;
+
+                               status = "disabled";
+
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+                                               dsi1_in: endpoint {
+                                                       remote-endpoint = <&mdp5_intf2_out>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+                                               dsi1_out: endpoint {
+                                               };
+                                       };
+                               };
+                       };
+
+                       dsi1_phy: phy@fd923000 {
+                               compatible = "qcom,dsi-phy-28nm-hpm";
+                               reg = <0xfd923000 0xd4>,
+                                     <0xfd923100 0x280>,
+                                     <0xfd923380 0x30>;
+                               reg-names = "dsi_pll",
+                                           "dsi_phy",
+                                           "dsi_phy_regulator";
+
+                               #clock-cells = <1>;
+                               #phy-cells = <0>;
+
+                               clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
+                               clock-names = "iface", "ref";
+
+                               status = "disabled";
+                       };
                };
 
                cci: cci@fda0c000 {