SAI_XCLRFR_MASK);
if (flags & SAI_XIMR_OVRUDRIE) {
- dev_err(&pdev->dev, "IT %s\n",
+ dev_err(&pdev->dev, "IRQ %s\n",
STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
status = SNDRV_PCM_STATE_XRUN;
}
if (flags & SAI_XIMR_MUTEDETIE)
- dev_dbg(&pdev->dev, "IT mute detected\n");
+ dev_dbg(&pdev->dev, "IRQ mute detected\n");
if (flags & SAI_XIMR_WCKCFGIE) {
- dev_err(&pdev->dev, "IT wrong clock configuration\n");
+ dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
status = SNDRV_PCM_STATE_DISCONNECTED;
}
if (flags & SAI_XIMR_CNRDYIE)
- dev_warn(&pdev->dev, "IT Codec not ready\n");
+ dev_err(&pdev->dev, "IRQ Codec not ready\n");
if (flags & SAI_XIMR_AFSDETIE) {
- dev_warn(&pdev->dev, "IT Anticipated frame synchro\n");
+ dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
status = SNDRV_PCM_STATE_XRUN;
}
if (flags & SAI_XIMR_LFSDETIE) {
- dev_warn(&pdev->dev, "IT Late frame synchro\n");
+ dev_err(&pdev->dev, "IRQ Late frame synchro\n");
status = SNDRV_PCM_STATE_XRUN;
}
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
int slotr, slotr_mask, slot_size;
- dev_dbg(cpu_dai->dev, "masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
+ dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
tx_mask, rx_mask, slots, slot_width);
switch (slot_width) {
ret = clk_prepare_enable(sai->sai_ck);
if (ret < 0) {
- dev_err(cpu_dai->dev, "failed to enable clock: %d\n", ret);
+ dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
return ret;
}
SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
}
- dev_dbg(cpu_dai->dev, "slots %d, slot width %d\n",
+ dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
sai->slots, sai->slot_width);
return 0;
frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
- dev_dbg(cpu_dai->dev, "frame length %d, frame active %d\n",
+ dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
sai->fs_length, fs_active);
regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
if (IS_ERR(sai->sai_ck)) {
- dev_err(&pdev->dev, "missing kernel clock sai_ck\n");
+ dev_err(&pdev->dev, "Missing kernel clock sai_ck\n");
return PTR_ERR(sai->sai_ck);
}
ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
IRQF_SHARED, dev_name(&pdev->dev), sai);
if (ret) {
- dev_err(&pdev->dev, "irq request returned %d\n", ret);
+ dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
return ret;
}
ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
&stm32_sai_pcm_config, 0);
if (ret) {
- dev_err(&pdev->dev, "could not register pcm dma\n");
+ dev_err(&pdev->dev, "Could not register pcm dma\n");
return ret;
}
module_platform_driver(stm32_sai_sub_driver);
MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
-MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
+MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
MODULE_ALIAS("platform:st,stm32-sai-sub");
MODULE_LICENSE("GPL v2");