def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE3, AMDGPUcvt_f32_ubyte3>;
def : GINodeEquiv<G_AMDGPU_CVT_PK_I16_I32, AMDGPUpk_i16_i32_impl>;
-def : GINodeEquiv<G_AMDGPU_MED3_S32, AMDGPUsmed3>;
+def : GINodeEquiv<G_AMDGPU_MED3, AMDGPUsmed3>;
def : GINodeEquiv<G_AMDGPU_ATOMIC_CMPXCHG, AMDGPUatomic_cmp_swap>;
def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD, SIbuffer_load>;
auto Bitcast = B.buildBitcast({S32}, CvtPk);
- auto Med3 = B.buildInstr(AMDGPU::G_AMDGPU_MED3_S32,
+ auto Med3 = B.buildInstr(AMDGPU::G_AMDGPU_MED3,
{S32},
{MinBoundaryDst.getReg(0), Bitcast.getReg(0), MaxBoundaryDst.getReg(0)},
MI.getFlags());
- auto Trunc = B.buildTrunc(LLT::scalar(16), Med3);
- B.buildCopy(MI.getOperand(0).getReg(), Trunc);
+ B.buildTrunc(MI.getOperand(0).getReg(), Med3);
MI.eraseFromParent();
}
case AMDGPU::G_AMDGPU_CVT_F32_UBYTE2:
case AMDGPU::G_AMDGPU_CVT_F32_UBYTE3:
case AMDGPU::G_AMDGPU_CVT_PK_I16_I32:
- case AMDGPU::G_AMDGPU_MED3_S32:
+ case AMDGPU::G_AMDGPU_MED3:
return getDefaultMappingVOP(MI);
case AMDGPU::G_UMULH:
case AMDGPU::G_SMULH: {
let hasSideEffects = 0;
}
-def G_AMDGPU_MED3_S32 : AMDGPUGenericInstruction {
+def G_AMDGPU_MED3 : AMDGPUGenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
let hasSideEffects = 0;