remoteproc: qcom: q6v5-mss: Improve readability of reset_assert

Define AXI_GATING_VALID_OVERRIDE and fixup comments to improve readability
of Q6 modem reset sequence on SC7180 SoCs.

Reviewed-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200123131236.1078-3-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index 89ab96c..a1cc9cb 100644 (file)
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -71,6 +71,7 @@
 #define NAV_AXI_HALTREQ_BIT            BIT(0)
 #define NAV_AXI_HALTACK_BIT            BIT(1)
 #define NAV_AXI_IDLE_BIT               BIT(2)
+#define AXI_GATING_VALID_OVERRIDE      BIT(0)
 
 #define HALT_ACK_TIMEOUT_US            100000
 #define NAV_HALT_ACK_TIMEOUT_US                200
@@ -415,16 +416,24 @@ static int q6v5_reset_assert(struct q6v5 *qproc)
                ret = reset_control_reset(qproc->mss_restart);
                reset_control_deassert(qproc->pdc_reset);
        } else if (qproc->has_halt_nav) {
-               /* SWAR using CONN_BOX_SPARE_0 for pipeline glitch issue */
+               /*
+                * When the AXI pipeline is being reset with the Q6 modem partly
+                * operational there is possibility of AXI valid signal to
+                * glitch, leading to spurious transactions and Q6 hangs. A work
+                * around is employed by asserting the AXI_GATING_VALID_OVERRIDE
+                * BIT before triggering Q6 MSS reset. Both the HALTREQ and
+                * AXI_GATING_VALID_OVERRIDE are withdrawn post MSS assert
+                * followed by a MSS deassert, while holding the PDC reset.
+                */
                reset_control_assert(qproc->pdc_reset);
                regmap_update_bits(qproc->conn_map, qproc->conn_box,
-                                  BIT(0), BIT(0));
+                                  AXI_GATING_VALID_OVERRIDE, 1);
                regmap_update_bits(qproc->halt_nav_map, qproc->halt_nav,
                                   NAV_AXI_HALTREQ_BIT, 0);
                reset_control_assert(qproc->mss_restart);
                reset_control_deassert(qproc->pdc_reset);
                regmap_update_bits(qproc->conn_map, qproc->conn_box,
-                                  BIT(0), 0);
+                                  AXI_GATING_VALID_OVERRIDE, 0);
                ret = reset_control_deassert(qproc->mss_restart);
        } else {
                ret = reset_control_assert(qproc->mss_restart);