e1000e: comment corrections

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c
index 227f3d0..f6f3a22 100644 (file)
--- a/drivers/net/e1000e/82571.c
+++ b/drivers/net/e1000e/82571.c
@@ -1551,7 +1551,7 @@ bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
  *  @hw: pointer to the HW structure
  *  @state: enable/disable locally administered address
  *
- *  Enable/Disable the current locally administers address state.
+ *  Enable/Disable the current locally administered address state.
  **/
 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
 {

diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index fbbc6dd..1ce2bf9 100644 (file)
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -1747,7 +1747,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
        if (hsfsts.hsf_status.flcinprog == 0) {
                /*
                 * There is no cycle running at present,
-                * so we can start a cycle
+                * so we can start a cycle.
                 * Begin by setting Flash Cycle Done.
                 */
                hsfsts.hsf_status.flcdone = 1;
@@ -1755,7 +1755,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
                ret_val = 0;
        } else {
                /*
-                * otherwise poll for sometime so the current
+                * Otherwise poll for sometime so the current
                 * cycle has a chance to end before giving up.
                 */
                for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
@@ -2645,7 +2645,6 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
                ctrl |= E1000_CTRL_PHY_RST;
        }
        ret_val = e1000_acquire_swflag_ich8lan(hw);
-       /* Whether or not the swflag was acquired, we need to reset the part */
        e_dbg("Issuing a global reset to ich8lan\n");
        ew32(CTRL, (ctrl | E1000_CTRL_RST));
        msleep(20);

diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c
index e3976ea..a86c175 100644 (file)
--- a/drivers/net/e1000e/lib.c
+++ b/drivers/net/e1000e/lib.c
@@ -1086,7 +1086,6 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
                 *   1   |    1    |   0   |    0    | e1000_fc_none
                 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
                 *
-                *
                 * Are both PAUSE bits set to 1?  If so, this implies
                 * Symmetric Flow Control is enabled at both ends.  The
                 * ASM_DIR bits are irrelevant per the spec.
@@ -1124,7 +1123,6 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
                 *-------|---------|-------|---------|--------------------
                 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
-                *
                 */
                else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
                          (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
@@ -1140,7 +1138,6 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
                 *-------|---------|-------|---------|--------------------
                 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
-                *
                 */
                else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
                         (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
@@ -2363,7 +2360,7 @@ static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
 }
 
 /**
- *  e1000_mng_host_if_write - Writes to the manageability host interface
+ *  e1000_mng_host_if_write - Write to the manageability host interface
  *  @hw: pointer to the HW structure
  *  @buffer: pointer to the host interface buffer
  *  @length: size of the buffer

diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
index 140b23b..1bc09b2 100644 (file)
--- a/drivers/net/e1000e/phy.c
+++ b/drivers/net/e1000e/phy.c
@@ -153,10 +153,10 @@ s32 e1000e_get_phy_id(struct e1000_hw *hw)
                        goto out;
 
                /*
-                * If the PHY ID is still unknown, we may have an 82577i
-                * without link.  We will try again after setting Slow
-                * MDIC mode. No harm in trying again in this case since
-                * the PHY ID is unknown at this point anyway
+                * If the PHY ID is still unknown, we may have an 82577
+                * without link.  We will try again after setting Slow MDIC
+                * mode. No harm in trying again in this case since the PHY
+                * ID is unknown at this point anyway.
                 */
                ret_val = phy->ops.acquire(hw);
                if (ret_val)
@@ -1744,7 +1744,7 @@ out:
  *  The automatic gain control (agc) normalizes the amplitude of the
  *  received signal, adjusting for the attenuation produced by the
  *  cable.  By reading the AGC registers, which represent the
- *  combination of course and fine gain value, the value can be put
+ *  combination of coarse and fine gain value, the value can be put
  *  into a lookup table to obtain the approximate cable length
  *  for each channel.
  **/
@@ -1769,7 +1769,7 @@ s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
 
                /*
                 * Getting bits 15:9, which represent the combination of
-                * course and fine gain values.  The result is a number
+                * coarse and fine gain values.  The result is a number
                 * that can be put into the lookup table to obtain the
                 * approximate cable length.
                 */
@@ -2511,7 +2511,7 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
                ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
                                                   data);
        } else {
-               /* Read the page 800 value using opcode 0x12 */
+               /* Write the page 800 value using opcode 0x12 */
                ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
                                                    *data);
        }