&& (unsigned) (INTVAL (op) + 0x1000) < 0x2000));
}
+/* Return true if OP is a register, or is a CONST_INT that can fit in a 5
+ bit unsigned immediate field. This is an acceptable SImode operand for
+ the count field of shift instructions. */
+
+int
+shift_operand (op, mode)
+ rtx op;
+ enum machine_mode mode;
+{
+ return (register_operand (op, mode)
+ || (GET_CODE (op) == CONST_INT && (unsigned) (INTVAL (op)) < 32));
+}
+
/* Return truth value of whether OP is a integer which fits the
range constraining immediate operands in most three-address insns,
which have a 13 bit immediate field. */
(define_insn "ashlsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashift:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "arith_operand" "rI")))]
+ (match_operand:SI 2 "shift_operand" "rI")))]
""
"sll %1,%2,%0")
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "arith_operand" "rI")))]
+ (match_operand:SI 2 "shift_operand" "rI")))]
""
"sra %1,%2,%0")
(define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "arith_operand" "rI")))]
+ (match_operand:SI 2 "shift_operand" "rI")))]
""
"srl %1,%2,%0")
\f