drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203
authorRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Wed, 29 Mar 2023 21:23:35 +0000 (18:23 -0300)
committerMatt Roper <matthew.d.roper@intel.com>
Thu, 30 Mar 2023 19:47:26 +0000 (12:47 -0700)
Both workarounds require the same implementation and apply to MTL P and
M from stepping A0 to B0 (exclusive).

v2:
  - Remove unrelated brace removal. (Matt)

Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230329212336.106161-2-gustavo.sousa@intel.com
drivers/gpu/drm/i915/gt/intel_gt_regs.h
drivers/gpu/drm/i915/gt/intel_workarounds.c

index 97a6094..0145779 100644 (file)
 #define   ENABLE_SMALLPL                       REG_BIT(15)
 #define   SC_DISABLE_POWER_OPTIMIZATION_EBB    REG_BIT(9)
 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG    REG_BIT(5)
+#define   MTL_DISABLE_SAMPLER_SC_OOO           REG_BIT(3)
 
 #define GEN9_HALF_SLICE_CHICKEN7               MCR_REG(0xe194)
 #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA      REG_BIT(15)
index 60e9cf2..f22a43d 100644 (file)
@@ -3052,6 +3052,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
        add_render_compute_tuning_settings(i915, wal);
 
        if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+           IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+               /*
+                * Wa_14017066071
+                * Wa_14017654203
+                */
+               wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
+                                MTL_DISABLE_SAMPLER_SC_OOO);
+
+       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
            IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
            IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
            IS_DG2_G11(i915) || IS_DG2_G12(i915)) {