staging: r8188eu: remove macro PHY_SetBBReg

The macro PHY_SetBBReg just re-defines rtl8188e_PHY_SetBBReg().
Call rtl8188e_PHY_SetBBReg() directly and remove the macro.

Signed-off-by: Michael Straube <straube.linux@gmail.com>
Link: https://lore.kernel.org/r/20211205171342.20551-6-straube.linux@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/r8188eu/hal/odm_interface.c b/drivers/staging/r8188eu/hal/odm_interface.c
index df981ca..04c2dc3 100644 (file)
--- a/drivers/staging/r8188eu/hal/odm_interface.c
+++ b/drivers/staging/r8188eu/hal/odm_interface.c
@@ -7,7 +7,7 @@
 void ODM_SetMACReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask, u32 Data)
 {
        struct adapter *Adapter = pDM_Odm->Adapter;
-       PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
+       rtl8188e_PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
 }
 
 u32 ODM_GetMACReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask)
@@ -19,7 +19,7 @@ u32 ODM_GetMACReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask)
 void ODM_SetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask, u32 Data)
 {
        struct adapter *Adapter = pDM_Odm->Adapter;
-       PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
+       rtl8188e_PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
 }
 
 u32 ODM_GetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask)

diff --git a/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c b/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c
index 99096a5..bf706e4 100644 (file)
--- a/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c
+++ b/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c
@@ -169,10 +169,10 @@ phy_RFSerialRead(
 
        tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;        /* T65 RF */
 
-       PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong & (~bLSSIReadEdge));
+       rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong & (~bLSSIReadEdge));
        udelay(10);/*  PlatformStallExecution(10); */
 
-       PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
+       rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
        udelay(100);/* PlatformStallExecution(100); */
 
        udelay(10);/* PlatformStallExecution(10); */
@@ -263,7 +263,7 @@ phy_RFSerialWrite(
        /*  */
        /*  Write Operation */
        /*  */
-       PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
+       rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 }
 
 /**
@@ -567,7 +567,7 @@ PHY_BBConfig8188E(
 
        /*  write 0x24[16:11] = 0x24[22:17] = CrystalCap */
        CrystalCap = pHalData->CrystalCap & 0x3F;
-       PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6)));
+       rtl8188e_PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6)));
 
        return rtStatus;
 }
@@ -704,17 +704,17 @@ _PHY_SetBWMode92C(
        switch (pHalData->CurrentChannelBW) {
        /* 20 MHz channel*/
        case HT_CHANNEL_WIDTH_20:
-               PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
-               PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
+               rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
+               rtl8188e_PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
                break;
        /* 40 MHz channel*/
        case HT_CHANNEL_WIDTH_40:
-               PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
-               PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
+               rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
+               rtl8188e_PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
                /*  Set Control channel to upper or lower. These settings are required only for 40MHz */
-               PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1));
-               PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
-               PHY_SetBBReg(Adapter, 0x818, (BIT(26) | BIT(27)),
+               rtl8188e_PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1));
+               rtl8188e_PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
+               rtl8188e_PHY_SetBBReg(Adapter, 0x818, (BIT(26) | BIT(27)),
                             (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
                break;
        default:

diff --git a/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c b/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c
index 45ab988..3d54fd0 100644 (file)
--- a/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c
+++ b/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c
@@ -148,15 +148,15 @@ rtl8188e_PHY_RF6052SetCckTxPower(
 
        /*  rf-A cck tx power */
        tmpval = TxAGC[RF_PATH_A] & 0xff;
-       PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
+       rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
        tmpval = TxAGC[RF_PATH_A] >> 8;
-       PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
+       rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
 
        /*  rf-B cck tx power */
        tmpval = TxAGC[RF_PATH_B] >> 24;
-       PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
+       rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
        tmpval = TxAGC[RF_PATH_B] & 0x00ffffff;
-       PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
+       rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
 }      /* PHY_RF6052SetCckTxPower */
 
 /*  */
@@ -298,7 +298,7 @@ static void writeOFDMPowerReg88E(struct adapter *Adapter, u8 index, u32 *pValue)
                else
                        regoffset = regoffset_b[index];
 
-               PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal);
+               rtl8188e_PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal);
 
                /*  201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
                if (regoffset == rTxAGC_A_Mcs07_Mcs04 || regoffset == rTxAGC_B_Mcs07_Mcs04) {
@@ -392,18 +392,18 @@ static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
        u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
 
        /*----Set RF_ENV enable----*/
-       PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1);
+       rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1);
        udelay(1);/* PlatformStallExecution(1); */
 
        /*----Set RF_ENV output high----*/
-       PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
+       rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
        udelay(1);/* PlatformStallExecution(1); */
 
        /* Set bit number of Address and Data for RF register */
-       PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);  /*  Set 1 to 4 bits for 8255 */
+       rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /*  Set 1 to 4 bits for 8255 */
        udelay(1);/* PlatformStallExecution(1); */
 
-       PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);     /*  Set 0 to 12  bits for 8255 */
+       rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);    /*  Set 0 to 12  bits for 8255 */
        udelay(1);/* PlatformStallExecution(1); */
 
        /*----Initialize RF fom connfiguration file----*/
@@ -411,7 +411,7 @@ static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
                rtStatus = _FAIL;
 
        /*----Restore RFENV control type----*/;
-       PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
+       rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
 
        if (rtStatus != _SUCCESS)
                goto phy_RF6052_Config_ParaFile_Fail;

diff --git a/drivers/staging/r8188eu/hal/usb_halinit.c b/drivers/staging/r8188eu/hal/usb_halinit.c
index 41b75aa..66cdf8a 100644 (file)
--- a/drivers/staging/r8188eu/hal/usb_halinit.c
+++ b/drivers/staging/r8188eu/hal/usb_halinit.c
@@ -556,8 +556,8 @@ static void _BeaconFunctionEnable(struct adapter *Adapter,
 /*  Set CCK and OFDM Block "ON" */
 static void _BBTurnOnBlock(struct adapter *Adapter)
 {
-       PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
-       PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
+       rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
+       rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
 }
 
 enum {
@@ -574,7 +574,7 @@ static void _InitAntenna_Selection(struct adapter *Adapter)
        DBG_88E("==>  %s ....\n", __func__);
 
        rtw_write32(Adapter, REG_LEDCFG0, rtw_read32(Adapter, REG_LEDCFG0) | BIT(23));
-       PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT(13), 0x01);
+       rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT(13), 0x01);
 
        if (PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
                haldata->CurAntenna = Antenna_A;

diff --git a/drivers/staging/r8188eu/include/Hal8188EPhyCfg.h b/drivers/staging/r8188eu/include/Hal8188EPhyCfg.h
index a60eb2e..30ede08 100644 (file)
--- a/drivers/staging/r8188eu/include/Hal8188EPhyCfg.h
+++ b/drivers/staging/r8188eu/include/Hal8188EPhyCfg.h
@@ -136,7 +136,5 @@ void storePwrIndexDiffRateOffset(struct adapter *adapter, u32 regaddr,
 
 #define PHY_QueryBBReg(adapt, regaddr, mask)                   \
         rtl8188e_PHY_QueryBBReg((adapt), (regaddr), (mask))
-#define PHY_SetBBReg(adapt, regaddr, bitmask, data)            \
-        rtl8188e_PHY_SetBBReg((adapt), (regaddr), (bitmask), (data))
 
 #endif /*  __INC_HAL8192CPHYCFG_H */