drm/msm: dpu: Only check flush register against pending flushes

There exists a case where a flush of a plane/dma may have been triggered
& started from an async commit. If that plane/dma is subsequently disabled
by the next commit, the flush register will continue to hold the flush
bit for the disabled plane. Since the bit remains active,
pending_kickoff_cnt will never decrement and we'll miss frame_done
events.

This patch limits the check of flush_register to include only those bits
which have been updated with the latest commit.

Changes in v2:
- None

Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index b3c68c4..667f304 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -331,7 +331,7 @@ static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
        if (hw_ctl && hw_ctl->ops.get_flush_register)
                flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
 
-       if (flush_register == 0)
+       if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
                new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt,
                                -1, 0);
        spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);