sparc.c: Change return <exp> to <exp>; return; in functions returning void.

	* sparc.c: Change return <exp> to <exp>; return; in functions
 	returning void.
	* sparc.md: Add empty semicolon statement after final label in
	move expanders.

From-SVN: r21678

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7e6b5d0..7922056 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+Tue Aug 11 23:02:31 1998  John Carr  <jfc@mit.edu>
+
+       * sparc.c: Change return <exp> to <exp>; return; in functions
+       returning void.
+       * sparc.md: Add empty semicolon statement after final label in
+       move expanders.
+
 Tue Aug 11 22:42:01 1998  David S. Miller  <davem@pierdol.cobaltmicro.com>
 
        * config/sparc/sparc.md (define_insn addx_extend): Rename to

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 32afae1..fcf7f6f 100644 (file)
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -1586,7 +1586,8 @@ sparc_emit_set_const64 (op0, op1)
        temp = op0;
       else
        temp = gen_reg_rtx (DImode);
-      return sparc_emit_set_symbolic_const64 (op0, op1, temp);
+      sparc_emit_set_symbolic_const64 (op0, op1, temp);
+      return;
     }
 
   if (GET_CODE (op1) == CONST_DOUBLE)
@@ -1716,8 +1717,11 @@ sparc_emit_set_const64 (op0, op1)
    */
   if (high_bits == 0
       || high_bits == 0xffffffff)
-    return sparc_emit_set_const64_quick1 (op0, temp, low_bits,
-                                         (high_bits == 0xffffffff));
+    {
+      sparc_emit_set_const64_quick1 (op0, temp, low_bits,
+                                    (high_bits == 0xffffffff));
+      return;
+    }
 
   /* 1) sethi  %hi(high_bits), %reg
    *    or     %reg, %lo(high_bits), %reg
@@ -1726,7 +1730,10 @@ sparc_emit_set_const64 (op0, op1)
   if (low_bits == 0
       || (SPARC_SIMM13_P(low_bits)
          && ((HOST_WIDE_INT)low_bits > 0)))
-    return sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
+    {
+      sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
+      return;
+    }
 
   /* Now, try 3-insn sequences.  But first we may be able to do something
      quick when the constant is negated, so try that.  */
@@ -1788,9 +1795,10 @@ sparc_emit_set_const64 (op0, op1)
       if (hi & lo)
        abort();
       focus_bits = (hi | lo);
-      return sparc_emit_set_const64_quick2 (op0, temp,
-                                           focus_bits, 0,
-                                           lowest_bit_set);
+      sparc_emit_set_const64_quick2 (op0, temp,
+                                    focus_bits, 0,
+                                    lowest_bit_set);
+      return;
     }
 
   /* The easiest way when all else fails, is full decomposition. */

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 2245b36..76918b6 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1934,6 +1934,7 @@
   /* All QI constants require only one insn, so proceed.  */
 
  movqi_is_ok:
+  ;
 }")
 
 (define_insn "*movqi_insn"
@@ -2002,6 +2003,7 @@
       DONE;
     }
  movhi_is_ok:
+  ;
 }")
 
 (define_insn "*movhi_insn"
@@ -2106,6 +2108,7 @@
       DONE;
     }
  movsi_is_ok:
+  ;
 }")
 
 ;; Special LIVE_G0 pattern to obtain zero in a register.
@@ -2290,6 +2293,7 @@
     }
 
  movdi_is_ok:
+  ;
 }")
 
 ;; Be careful, fmovd does not exist when !arch64.
@@ -2764,6 +2768,7 @@
     }
 
  movsf_is_ok:
+  ;
 }")
 
 (define_insn "*movsf_insn"
@@ -2849,6 +2854,7 @@
     }
 
  movdf_is_ok:
+  ;
 }")
 
 ;; Be careful, fmovd does not exist when !arch64.
@@ -3072,7 +3078,8 @@
        }
     }
 
-movtf_is_ok:
+ movtf_is_ok:
+  ;
 }")
 
 ;; Be careful, fmovq and {st,ld}{x,q} do not exist when !arch64 so