#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
#endif
+ if (of_property_read_bool(np, "brcm,gpio-direct"))
+ flags |= BGPIOF_REG_DIRECT;
of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
bank_width) {
}
gc->owner = THIS_MODULE;
- gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
+ gc->label = devm_kasprintf(dev, GFP_KERNEL, "gpio-brcmstb@%zx",
+ (size_t)res->start +
+ GIO_BANK_OFF(bank->id, 0));
if (!gc->label) {
err = -ENOMEM;
goto fail;
gc->of_gpio_n_cells = 2;
gc->of_xlate = brcmstb_gpio_of_xlate;
/* not all ngpio lines are valid, will use bank width later */
- gc->ngpio = MAX_GPIO_PER_BANK;
+ gc->ngpio = bank_width;
gc->offset = bank->id * MAX_GPIO_PER_BANK;
if (priv->parent_irq > 0)
gc->to_irq = brcmstb_gpio_to_irq;
* Mask all interrupts by default, since wakeup interrupts may
* be retained from S5 cold boot
*/
- need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
- gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
+ if (priv->parent_irq > 0) {
+ need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
+ gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
+ }
err = gpiochip_add_data(gc, bank);
if (err) {
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}
+static void bgpio_set_direct(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+ unsigned long mask = bgpio_line2mask(gc, gpio);
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
+
+ gc->bgpio_data = gc->read_reg(gc->reg_dat);
+
+ if (val)
+ gc->bgpio_data |= mask;
+ else
+ gc->bgpio_data &= ~mask;
+
+ gc->write_reg(gc->reg_dat, gc->bgpio_data);
+
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+}
+
static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
int val)
{
gc->write_reg(gc->reg_clr, clear_mask);
}
+static void bgpio_set_multiple_direct(struct gpio_chip *gc,
+ unsigned long *mask,
+ unsigned long *bits)
+{
+ unsigned long flags;
+ unsigned long set_mask, clear_mask;
+
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
+
+ bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
+
+ gc->bgpio_data = gc->read_reg(gc->reg_dat);
+
+ gc->bgpio_data |= set_mask;
+ gc->bgpio_data &= ~clear_mask;
+
+ gc->write_reg(gc->reg_dat, gc->bgpio_data);
+
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+}
+
static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
return 0;
return 0;
}
+static int bgpio_dir_in_direct(struct gpio_chip *gc, unsigned int gpio)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
+
+ if (gc->reg_dir_in)
+ gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
+ if (gc->reg_dir_out)
+ gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
+
+ gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
+
+ if (gc->reg_dir_in)
+ gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
+ if (gc->reg_dir_out)
+ gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
+
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+
+ return 0;
+}
+
static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
{
/* Return 0 if output, 1 if input */
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}
+static void bgpio_dir_out_direct(struct gpio_chip *gc, unsigned int gpio,
+ int val)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
+
+ if (gc->reg_dir_in)
+ gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
+ if (gc->reg_dir_out)
+ gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
+
+ gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
+
+ if (gc->reg_dir_in)
+ gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
+ if (gc->reg_dir_out)
+ gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
+
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+}
+
static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,
int val)
{
return 0;
}
+static int bgpio_dir_out_dir_first_direct(struct gpio_chip *gc,
+ unsigned int gpio, int val)
+{
+ bgpio_dir_out_direct(gc, gpio, val);
+ gc->set(gc, gpio, val);
+ return 0;
+}
+
+static int bgpio_dir_out_val_first_direct(struct gpio_chip *gc,
+ unsigned int gpio, int val)
+{
+ gc->set(gc, gpio, val);
+ bgpio_dir_out_direct(gc, gpio, val);
+ return 0;
+}
+
static int bgpio_setup_accessors(struct device *dev,
struct gpio_chip *gc,
bool byte_be)
} else if (flags & BGPIOF_NO_OUTPUT) {
gc->set = bgpio_set_none;
gc->set_multiple = NULL;
+ } else if (flags & BGPIOF_REG_DIRECT) {
+ gc->set = bgpio_set_direct;
+ gc->set_multiple = bgpio_set_multiple_direct;
} else {
gc->set = bgpio_set;
gc->set_multiple = bgpio_set_multiple;
if (dirout || dirin) {
gc->reg_dir_out = dirout;
gc->reg_dir_in = dirin;
- if (flags & BGPIOF_NO_SET_ON_INPUT)
- gc->direction_output = bgpio_dir_out_dir_first;
- else
- gc->direction_output = bgpio_dir_out_val_first;
- gc->direction_input = bgpio_dir_in;
+ if (flags & BGPIOF_REG_DIRECT) {
+ if (flags & BGPIOF_NO_SET_ON_INPUT)
+ gc->direction_output =
+ bgpio_dir_out_dir_first_direct;
+ else
+ gc->direction_output =
+ bgpio_dir_out_val_first_direct;
+ gc->direction_input = bgpio_dir_in_direct;
+ } else {
+ if (flags & BGPIOF_NO_SET_ON_INPUT)
+ gc->direction_output = bgpio_dir_out_dir_first;
+ else
+ gc->direction_output = bgpio_dir_out_val_first;
+ gc->direction_input = bgpio_dir_in;
+ }
gc->get_direction = bgpio_get_dir;
} else {
if (flags & BGPIOF_NO_OUTPUT)