{
struct comphy_map *ptr_comphy_map;
void __iomem *comphy_base_addr, *hpipe_base_addr;
- u32 comphy_max_count, lane, ret = 0;
+ u32 comphy_max_count, lane, id, ret = 0;
u32 pcie_width = 0;
u32 mode;
break;
case COMPHY_TYPE_SGMII0:
case COMPHY_TYPE_SGMII1:
- if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
- debug("Warning: ");
- debug("SGMII PHY speed in lane %d is invalid,",
- lane);
- debug(" set PHY speed to 1.25G\n");
- ptr_comphy_map->speed = COMPHY_SPEED_1_25G;
- }
-
- /*
- * UINIT_ID not relevant for SGMII0 and SGMII1 - will be
- * ignored by firmware
- */
- mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE,
- COMPHY_UNIT_ID0,
- ptr_comphy_map->speed);
- ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
- ptr_chip_cfg->comphy_base_addr, lane,
- mode);
- break;
case COMPHY_TYPE_SGMII2:
+ /* Calculate SGMII ID */
+ id = ptr_comphy_map->type - COMPHY_TYPE_SGMII0;
+
if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
lane);
ptr_comphy_map->speed = COMPHY_SPEED_1_25G;
}
- mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE,
- COMPHY_UNIT_ID2,
+ mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, id,
ptr_comphy_map->speed);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,