if ((amdgpu_in_reset(adev) &&
ras && adev->ras_enabled &&
(adev->asic_type == CHIP_ARCTURUS ||
- adev->asic_type == CHIP_VEGA20)) ||
- (adev->in_runpm &&
- adev->asic_type >= CHIP_NAVI10 &&
- adev->asic_type <= CHIP_NAVI12)) {
+ adev->asic_type == CHIP_VEGA20))) {
ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
if (ret) {
DRM_WARN("Failed to set MP1 state prepare for reload\n");
return 0;
}
-static int navi10_set_mp1_state(struct smu_context *smu,
- enum pp_mp1_state mp1_state)
-{
- struct amdgpu_device *adev = smu->adev;
- uint32_t mp1_fw_flags;
- int ret = 0;
-
- ret = smu_cmn_set_mp1_state(smu, mp1_state);
- if (ret)
- return ret;
-
- if (mp1_state == PP_MP1_STATE_UNLOAD) {
- mp1_fw_flags = RREG32_PCIE(MP1_Public |
- (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
-
- mp1_fw_flags &= ~MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK;
-
- WREG32_PCIE(MP1_Public |
- (smnMP1_FIRMWARE_FLAGS & 0xffffffff), mp1_fw_flags);
- }
-
- return 0;
-}
-
static int navi10_setup_pptable(struct smu_context *smu)
{
int ret = 0;
.get_fan_parameters = navi10_get_fan_parameters,
.post_init = navi10_post_smu_init,
.interrupt_work = smu_v11_0_interrupt_work,
- .set_mp1_state = navi10_set_mp1_state,
+ .set_mp1_state = smu_cmn_set_mp1_state,
};
void navi10_set_ppt_funcs(struct smu_context *smu)