clk:starfive:Adjust clocks' flag

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index 483cd655c9e63bfbe05e6e8bab35b4f538457632..0676b470b39a6325a64cf8ea32d5a0fb2c06fd60 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -37,7 +37,7 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
        JH7110_GATE(JH7110_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_STG_AXIAHB),
        JH7110__DIV(JH7110_APB_BUS_FUNC, "apb_bus_func",
                        8, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_APB0, "apb0", CLK_IS_CRITICAL, JH7110_APB_BUS),
+       JH7110_GATE(JH7110_APB0, "apb0", CLK_IGNORE_UNUSED, JH7110_APB_BUS),
        JH7110__DIV(JH7110_PLL0_DIV2, "pll0_div2", 2, JH7110_PLL0_OUT),
        JH7110__DIV(JH7110_PLL1_DIV2, "pll1_div2", 2, JH7110_PLL1_OUT),
        JH7110__DIV(JH7110_PLL2_DIV2, "pll2_div2", 2, JH7110_PLL2_OUT),
@@ -52,39 +52,39 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
                        JH7110_PLL2_OUT,
                        JH7110_PLL1_OUT),
        JH7110__DIV(JH7110_ISP_AXI, "isp_axi", 4, JH7110_ISP_2X),
-       JH7110_GDIV(JH7110_GCLK0, "gclk0", CLK_IS_CRITICAL,
+       JH7110_GDIV(JH7110_GCLK0, "gclk0", GATE_FLAG_NORMAL,
                        62, JH7110_PLL0_DIV2),
-       JH7110_GDIV(JH7110_GCLK1, "gclk1", CLK_IS_CRITICAL,
+       JH7110_GDIV(JH7110_GCLK1, "gclk1", GATE_FLAG_NORMAL,
                        62, JH7110_PLL1_DIV2),
-       JH7110_GDIV(JH7110_GCLK2, "gclk2", CLK_IS_CRITICAL,
+       JH7110_GDIV(JH7110_GCLK2, "gclk2", GATE_FLAG_NORMAL,
                        62, JH7110_PLL2_DIV2),
        /*u0_u7mc_sft7110*/
        JH7110_GATE(JH7110_U7_CORE_CLK, "u0_u7mc_sft7110_core_clk",
-                       CLK_IS_CRITICAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_CORE_CLK1, "u0_u7mc_sft7110_core_clk1",
-                       CLK_IS_CRITICAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_CORE_CLK2, "u0_u7mc_sft7110_core_clk2",
-                       CLK_IS_CRITICAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_CORE_CLK3, "u0_u7mc_sft7110_core_clk3",
-                       CLK_IS_CRITICAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_CORE_CLK4, "u0_u7mc_sft7110_core_clk4",
-                       CLK_IS_CRITICAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_DEBUG_CLK, "u0_u7mc_sft7110_debug_clk",
-                       CLK_IS_CRITICAL, JH7110_CPU_BUS),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_BUS),
        JH7110__DIV(JH7110_U7_RTC_TOGGLE, "u0_u7mc_sft7110_rtc_toggle",
                        6, JH7110_OSC),
        JH7110_GATE(JH7110_U7_TRACE_CLK0, "u0_u7mc_sft7110_trace_clk0",
-                       CLK_IS_CRITICAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_CLK1, "u0_u7mc_sft7110_trace_clk1",
-                       CLK_IS_CRITICAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_CLK2, "u0_u7mc_sft7110_trace_clk2",
-                       CLK_IS_CRITICAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_CLK3, "u0_u7mc_sft7110_trace_clk3",
-                       CLK_IS_CRITICAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_CLK4, "u0_u7mc_sft7110_trace_clk4",
-                       CLK_IS_CRITICAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_COM_CLK, "u0_u7mc_sft7110_trace_com_clk",
-                       CLK_IS_CRITICAL, JH7110_CPU_BUS),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_BUS),
        //NOC
        JH7110_GATE(JH7110_NOC_BUS_CLK_CPU_AXI,
                        "u0_sft7110_noc_bus_clk_cpu_axi",
@@ -338,9 +338,9 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
                        GATE_FLAG_NORMAL, JH7110_APB12),
        //UART
        JH7110_GATE(JH7110_UART0_CLK_APB, "u0_dw_uart_clk_apb",
-                       CLK_IS_CRITICAL, JH7110_APB0),
+                       CLK_IGNORE_UNUSED, JH7110_APB0),
        JH7110_GATE(JH7110_UART0_CLK_CORE, "u0_dw_uart_clk_core",
-                       CLK_IS_CRITICAL, JH7110_OSC),
+                       CLK_IGNORE_UNUSED, JH7110_OSC),
        JH7110_GATE(JH7110_UART1_CLK_APB, "u1_dw_uart_clk_apb",
                        GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GATE(JH7110_UART1_CLK_CORE, "u1_dw_uart_clk_core",