arm64: dts: imx8mq-evk: Add second PCIe port support

Enable the second PCIe port support on i.MX8MQ EVK board.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index e7f521a..99fed35 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -27,6 +27,17 @@
                clock-frequency = <100000000>;
        };
 
+       reg_pcie1: regulator-pcie {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_pcie1_reg>;
+               regulator-name = "MPCIE_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
        reg_usdhc2_vmmc: regulator-vsd-3v3 {
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_reg_usdhc2>;
@@ -328,6 +339,20 @@
        status = "okay";
 };
 
+&pcie1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie1>;
+       reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
+       clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
+                <&clk IMX8MQ_CLK_PCIE2_AUX>,
+                <&clk IMX8MQ_CLK_PCIE2_PHY>,
+                <&pcie0_refclk>;
+       clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+       vpcie-supply = <&reg_pcie1>;
+       vph-supply = <&vgen5_reg>;
+       status = "okay";
+};
+
 &pgc_gpu {
        power-supply = <&sw1a_reg>;
 };
@@ -483,6 +508,19 @@
                >;
        };
 
+       pinctrl_pcie1: pcie1grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B            0x76
+                       MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12             0x16
+               >;
+       };
+
+       pinctrl_pcie1_reg: pcie1reggrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10             0x16
+               >;
+       };
+
        pinctrl_qspi: qspigrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK       0x82