RADV_BO_PRIORITY_CS = 31,
};
+struct radv_winsys_gpuvm_fault_info {
+ uint64_t addr;
+ uint32_t status;
+ uint32_t vmhub;
+};
+
struct radeon_winsys {
void (*destroy)(struct radeon_winsys *ws);
const char *(*get_chip_name)(struct radeon_winsys *ws);
+ bool (*query_gpuvm_fault)(struct radeon_winsys *ws, struct radv_winsys_gpuvm_fault_info *fault_info);
+
VkResult (*buffer_create)(struct radeon_winsys *ws, uint64_t size, unsigned alignment, enum radeon_bo_domain domain,
enum radeon_bo_flag flags, unsigned priority, uint64_t address,
struct radeon_winsys_bo **out_bo);
return amdgpu_get_marketing_name(dev);
}
+static bool
+radv_amdgpu_winsys_query_gpuvm_fault(struct radeon_winsys *rws, struct radv_winsys_gpuvm_fault_info *fault_info)
+{
+ struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
+ struct drm_amdgpu_info_gpuvm_fault gpuvm_fault = {0};
+ int r;
+
+ r = amdgpu_query_info(ws->dev, AMDGPU_INFO_GPUVM_FAULT, sizeof(gpuvm_fault), &gpuvm_fault);
+ if (r < 0) {
+ fprintf(stderr, "radv/amdgpu: Failed to query the last GPUVM fault (%d).\n", r);
+ return false;
+ }
+
+ /* When the GPUVM fault status is 0, no faults happened. */
+ if (!gpuvm_fault.status)
+ return false;
+
+ fault_info->addr = gpuvm_fault.addr;
+ fault_info->status = gpuvm_fault.status;
+ fault_info->vmhub = gpuvm_fault.vmhub;
+
+ return true;
+}
+
static simple_mtx_t winsys_creation_mutex = SIMPLE_MTX_INITIALIZER;
static struct hash_table *winsyses = NULL;
ws->base.query_value = radv_amdgpu_winsys_query_value;
ws->base.read_registers = radv_amdgpu_winsys_read_registers;
ws->base.get_chip_name = radv_amdgpu_winsys_get_chip_name;
+ ws->base.query_gpuvm_fault = radv_amdgpu_winsys_query_gpuvm_fault;
ws->base.destroy = radv_amdgpu_winsys_destroy;
ws->base.get_fd = radv_amdgpu_winsys_get_fd;
ws->base.get_sync_types = radv_amdgpu_winsys_get_sync_types;