if (likely(!(agx_compiler_debug & AGX_DBG_NOOPT))) {
/* Dead code eliminate before instruction combining so use counts are
* right */
- agx_dce(ctx);
+ agx_dce(ctx, true);
agx_optimizer(ctx);
agx_opt_cse(ctx);
agx_lower_uniform_sources(ctx);
/* Dead code eliminate after instruction combining to get the benefit */
- agx_dce(ctx);
+ agx_dce(ctx, true);
agx_validate(ctx, "Optimization");
if (agx_should_dump(nir, AGX_DBG_SHADERS))
void agx_lower_pseudo(agx_context *ctx);
void agx_lower_uniform_sources(agx_context *ctx);
void agx_opt_cse(agx_context *ctx);
-void agx_dce(agx_context *ctx);
+void agx_dce(agx_context *ctx, bool partial);
void agx_ra(agx_context *ctx);
void agx_lower_64bit_postra(agx_context *ctx);
void agx_insert_waits(agx_context *ctx);
/* SSA-based scalar dead code elimination */
void
-agx_dce(agx_context *ctx)
+agx_dce(agx_context *ctx, bool partial)
{
bool progress;
do {
bool needed = false;
- agx_foreach_dest(I, d) {
+ agx_foreach_ssa_dest(I, d) {
/* Eliminate destinations that are never read, as RA needs to
* handle them specially. Visible only for instructions that write
* multiple destinations (splits) or that write a destination but
* cannot be DCE'd (atomics).
*/
- if ((I->dest[d].type == AGX_INDEX_NORMAL) &&
- !BITSET_TEST(seen, I->dest[d].value))
+ if (BITSET_TEST(seen, I->dest[d].value))
+ needed = true;
+ else if (partial)
I->dest[d] = agx_null();
-
- /* If the destination is actually needed, the instruction is too */
- needed |= (I->dest[d].type != AGX_INDEX_NULL);
}
if (!needed) {