E: arsenio@tin.it
D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more
+N: Andre Schwarz
+E: andre.schwarz@matrix-vision.de
+D: Support for Matrix Vision boards (MVBLM7)
+
N: Robert Schwebel
E: r.schwebel@pengutronix.de
D: Support for csb226, logodl and innokom boards (PXA2xx)
ML2 PPC4xx
+Andre Schwarz <andre.schwarz@matrix-vision.de>
+
+ mvblm7 MPC8343
+
Timur Tabi <timur@freescale.com>
MPC8349E-mITX MPC8349
MPC8360ERDK_66 \
MPC837XEMDS \
MPC837XERDB \
+ MVBLM7 \
sbc8349 \
TQM834x \
"
MPC837XERDB_config: unconfig
@$(MKCONFIG) -a MPC837XERDB ppc mpc83xx mpc837xerdb freescale
+MVBLM7_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7
+
sbc8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
}
-#if defined(CFG_DRAM_TEST)
-int
-testdram(void)
-{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
- uint *p;
-
- puts("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- puts("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- puts("SDRAM test passed.\n");
- return 0;
-}
-#endif
-
-
#if !defined(CONFIG_SPD_EEPROM)
/*
* Fixed sdram init -- doesn't use serial presence detect.
}
-#if defined(CFG_DRAM_TEST)
-int
-testdram(void)
-{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
- uint *p;
-
- puts("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- puts("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- puts("SDRAM test passed.\n");
- return 0;
-}
-#endif
-
-
#if !defined(CONFIG_SPD_EEPROM)
/*
* Fixed sdram init -- doesn't use serial presence detect.
--- /dev/null
+#
+# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o pci.o fpga.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+TEXT_BASE = 0xFFF00000
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include "fpga.h"
+#include "mvblm7.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+ fpga_null_fn,
+ fpga_config_fn,
+ fpga_status_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_null_fn,
+ fpga_null_fn,
+ 0
+};
+
+Altera_desc cyclone2 = {
+ Altera_CYC2,
+ passive_serial,
+ Altera_EP2C20_SIZE,
+ (void *) &altera_fns,
+ NULL,
+ 0
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvblm7_init_fpga(void)
+{
+ fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n",
+ gd->reloc_off);
+ fpga_init(gd->reloc_off);
+ fpga_add(fpga_altera, &cyclone2);
+ fpga_config_fn(0, 1, 0);
+ udelay(60);
+
+ return 1;
+}
+
+int fpga_null_fn(int cookie)
+{
+ return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+ volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+ u32 dvo = gpio->dat;
+
+ fpga_debug("SET config : %s\n", assert ? "low" : "high");
+ if (assert)
+ dvo |= FPGA_CONFIG;
+ else
+ dvo &= ~FPGA_CONFIG;
+
+ if (flush)
+ gpio->dat = dvo;
+
+ return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+ volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+ int result = 0;
+
+ udelay(10);
+ fpga_debug("CONF_DONE check ... ");
+ if (gpio->dat & FPGA_CONF_DONE) {
+ fpga_debug("high\n");
+ result = 1;
+ } else
+ fpga_debug("low\n");
+
+ return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+ volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+ int result = 0;
+
+ fpga_debug("STATUS check ... ");
+ if (gpio->dat & FPGA_STATUS) {
+ fpga_debug("high\n");
+ result = 1;
+ } else
+ fpga_debug("low\n");
+
+ return result;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+ u32 dvo = gpio->dat;
+
+ fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
+ if (assert_clk)
+ dvo |= FPGA_CCLK;
+ else
+ dvo &= ~FPGA_CCLK;
+
+ if (flush)
+ gpio->dat = dvo;
+
+ return assert_clk;
+}
+
+static inline int _write_fpga(u8 val, int dump)
+{
+ volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+ int i;
+ u32 dvo = gpio->dat;
+
+ if (dump)
+ fpga_debug(" %02x -> ", val);
+ for (i = 0; i < 8; i++) {
+ dvo &= ~FPGA_CCLK;
+ gpio->dat = dvo;
+ dvo &= ~FPGA_DIN;
+ if (dump)
+ fpga_debug("%d ", val&1);
+ if (val & 1)
+ dvo |= FPGA_DIN;
+ gpio->dat = dvo;
+ dvo |= FPGA_CCLK;
+ gpio->dat = dvo;
+ val >>= 1;
+ }
+ if (dump)
+ fpga_debug("\n");
+
+ return 0;
+}
+
+int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+{
+ unsigned char *data = (unsigned char *) buf;
+ int i;
+
+ fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+ for (i = 0; i < len; i++)
+ _write_fpga(data[i], 0);
+ fpga_debug("\n");
+
+ return FPGA_SUCCESS;
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvblm7_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
--- /dev/null
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#include <spi.h>
+#include <asm/mmu.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+#include "mvblm7.h"
+
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
+ u32 msize = 0;
+ u32 ddr_size;
+ u32 ddr_size_log2;
+
+ msize = CFG_DDR_SIZE;
+ for (ddr_size = msize << 20, ddr_size_log2 = 0;
+ (ddr_size > 1);
+ ddr_size = ddr_size >> 1, ddr_size_log2++) {
+ if (ddr_size & 1)
+ return -1;
+ }
+ im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+ im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
+ LAWAR_SIZE);
+
+ im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+ im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CFG_DDR_MODE;
+ im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+
+ udelay(300);
+
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+ return CFG_DDR_SIZE;
+}
+
+long int initdram(int board_type)
+{
+ volatile immap_t *im = (immap_t *) CFG_IMMR;
+ u32 msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+ return -1;
+
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+ msize = fixed_sdram();
+
+ /* return total bus RAM size(bytes) */
+ return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+ puts("Board: Matrix Vision mvBlueLYNX-M7 " MV_VERSION "\n");
+
+ return 0;
+}
+
+u8 *dhcp_vendorex_prep(u8 *e)
+{
+ char *ptr;
+
+ /* DHCP vendor-class-identifier = 60 */
+ ptr = getenv("dhcp_vendor-class-identifier");
+ if (ptr) {
+ *e++ = 60;
+ *e++ = strlen(ptr);
+ while (*ptr)
+ *e++ = *ptr++;
+ }
+ /* DHCP_CLIENT_IDENTIFIER = 61 */
+ ptr = getenv("dhcp_client_id");
+ if (ptr) {
+ *e++ = 61;
+ *e++ = strlen(ptr);
+ while (*ptr)
+ *e++ = *ptr++;
+ }
+
+ return e;
+}
+
+u8 *dhcp_vendorex_proc(u8 *popt)
+{
+ return NULL;
+}
+
+#ifdef CONFIG_HARD_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+
+ iopd->dat &= ~MVBLM7_MMC_CS;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+
+ iopd->dat |= ~MVBLM7_MMC_CS;
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+}
+
+#endif
--- /dev/null
+#ifndef __MVBC_H__
+#define __MVBC_H__
+
+#define MV_GPIO
+
+#define FPGA_CONFIG 0x80000000
+#define FPGA_CCLK 0x40000000
+#define FPGA_DIN 0x20000000
+#define FPGA_STATUS 0x10000000
+#define FPGA_CONF_DONE 0x08000000
+#define MMC_CS 0x04000000
+
+#define WD_WDI 0x00400000
+#define WD_TS 0x00200000
+#define MAN_RST 0x00100000
+
+#define MV_GPIO_DAT (WD_TS)
+#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|WD_TS|WD_WDI|MMC_CS)
+#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST)
+
+#endif
--- /dev/null
+echo
+echo "==== running autoscript ===="
+echo
+setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
+setenv ramkernel setenv kernel_boot \${loadaddr}
+setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
+setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
+setenv bootfromflash run flashkernel cpird ramparam bootdtb
+setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
+setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
+setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
+setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
+setenv set_static_ip setenv ipaddr \${static_ipaddr}
+setenv set_static_nm setenv netmask \${static_netmask}
+setenv set_static_gw setenv gatewayip \${static_gateway}
+setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
+setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
+if test ${autoscr_boot} != no;
+then
+ if test ${netboot} = yes;
+ then
+ bootp
+ if test $? = 0;
+ then
+ echo "=== bootp succeeded -> netboot ==="
+ run set_ip
+ run getdtb rundtb bootfromnet ramparam bootdtb
+ else
+ echo "=== netboot failed ==="
+ fi
+ fi
+ run set_static_ip set_static_nm set_static_gw set_ip
+ echo "=== bootfromflash ==="
+ run cpdtb rundtb bootfromflash
+else
+ echo "=== boot stopped with autoscr_boot no ==="
+fi
--- /dev/null
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#include <pci.h>
+#include <mpc83xx.h>
+#include <fpga.h>
+#include "mvblm7.h"
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvblm7_load_fpga(void)
+{
+ size_t data_size = 0;
+ void *fpga_data = NULL;
+ char *datastr = getenv("fpgadata");
+ char *sizestr = getenv("fpgadatasize");
+
+ if (datastr)
+ fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
+ if (sizestr)
+ data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
+
+ return fpga_load(0, fpga_data, data_size);
+}
+
+static struct pci_region pci_regions[] = {
+ {
+ bus_start: CFG_PCI1_MEM_BASE,
+ phys_start: CFG_PCI1_MEM_PHYS,
+ size: CFG_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CFG_PCI1_MMIO_BASE,
+ phys_start: CFG_PCI1_MMIO_PHYS,
+ size: CFG_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+ {
+ bus_start: CFG_PCI1_IO_BASE,
+ phys_start: CFG_PCI1_IO_PHYS,
+ size: CFG_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ }
+};
+
+void pci_init_board(void)
+{
+ char *s;
+ int i;
+ int warmboot;
+ int load_fpga;
+ volatile immap_t *immr;
+ volatile pcictrl83xx_t *pci_ctrl;
+ volatile gpio83xx_t *gpio;
+ volatile clk83xx_t *clk;
+ volatile law83xx_t *pci_law;
+ struct pci_region *reg[] = { pci_regions };
+
+ load_fpga = 1;
+ immr = (immap_t *) CFG_IMMR;
+ clk = (clk83xx_t *) &immr->clk;
+ pci_ctrl = immr->pci_ctrl;
+ pci_law = immr->sysconf.pcilaw;
+ gpio = (volatile gpio83xx_t *)&immr->gpio[0];
+
+ s = getenv("skip_fpga");
+ if (s) {
+ printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
+ load_fpga = 0;
+ }
+
+ gpio->dat = MV_GPIO_DAT;
+ gpio->odr = MV_GPIO_ODE;
+ if (load_fpga)
+ gpio->dir = MV_GPIO_OUT;
+ else
+ gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
+
+ printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
+ immr->sysconf.sicrl);
+
+ mvblm7_init_fpga();
+ if (load_fpga)
+ mvblm7_load_fpga();
+
+ /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
+ clk->occr = 0xc0000000;
+
+ pci_ctrl[0].gcr = 0;
+ udelay(2000);
+ pci_ctrl[0].gcr = 1;
+
+ for (i = 0; i < 1000; ++i)
+ udelay(1000);
+
+ pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
+
+ pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+ warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
+
+ mpc83xx_pci_init(1, reg, warmboot);
+}
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);
-#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
+/*
+ * End of addressable memory. This may be less than the actual
+ * amount of memory on the system if we're unable to keep all
+ * the memory mapped in.
+ */
+extern ulong get_effective_memsize(void);
+#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
/*
* Trap & Exception support
--- /dev/null
+Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
+-------------------------------------
+
+1. Board Description
+
+ The mvBL-M7 is a 120x120mm single board computing platform
+ with strong focus on stereo image processing applications.
+
+ Power Supply is either VDC 12-48V or Pover over Ethernet (PoE)
+ on any port (requires add-on board).
+
+2 System Components
+
+2.1 CPU
+ Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
+ 512MByte DDR-II memory @ 133MHz.
+ 8 MByte Nor Flash on local bus.
+ 2 Vitesse VSC8601 RGMII ethernet Phys.
+ 1 USB host controller over ULPI I/F.
+ 2 serial ports. Console running on ttyS0 @ 115200 8N1.
+ 1 SD-Card slot connected to SPI.
+ System configuration (HRCW) is taken from I2C EEPROM.
+
+2.2 PCI
+ A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
+
+2.3 FPGA
+ Altera Cyclone-II EP2C20/35 with PCI DMA engines.
+ Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
+ Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash.
+
+2.3.1 I/O @ FPGA
+ 2x8 Outputs : Infineon High-Side Switches to Main Supply.
+ 2x8 Inputs : Programmable input threshold + trigger capabilities
+ 2 dedicated flash interfaces for illuminator boards.
+ Cross trigger for chaining several boards.
+
+2.4 I2C
+ Bus1:
+ MAX5381 DAC @ 0x60 for 1st digital input threshold.
+ LM75 @ 0x90 for temperature monitoring.
+ EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
+ 1st image sensor interface (slave adresses depend on sensor)
+ Bus2:
+ MAX5381 DAC @ 0x60 for 2nd digital input threshold.
+ 2nd image sensor interface (slave adresses depend on sensor)
+
+3 Flash layout.
+
+ reset vector is 0xFFF00100, i.e. "HIGHBOOT".
+
+ FF800000 environment
+ FF802000 redundant environment
+ FF804000 u-boot script image
+ FF806000 redundant u-boot script image
+ FF808000 device tree blob
+ FF80A000 redundant device tree blob
+ FF80C000 tbd.
+ FF80E000 tbd.
+ FF810000 kernel
+ FFC00000 root FS
+ FFF00000 u-boot
+ FFF80000 FPGA raw bit file
+
+ mtd partitions are propagated to linux kernel via device tree blob.
+
+4 Booting
+
+ On startup the bootscript @ FF804000 is executed. This script can be
+ exchanged easily. Default boot mode is "boot from flash", i.e. system
+ works stand-alone.
+
+ This behaviour depends on some environment variables :
+
+ "netboot" : yes ->try dhcp/bootp and boot from network.
+ A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
+ DHCP server configuration, e.g. to provide different images to
+ different devices.
+
+ During netboot the system tries to get 3 image files:
+ 1. Kernel - name + data is given during BOOTP.
+ 2. Initrd - name is stored in "initrd_name"
+ 3. device tree blob - name is stored in "dtb_name"
+ Fallback files are the flash versions.
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_R 1
-#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
-#define CFG_ALT_MEMTEST
/*
* Base addresses -- Note these are effective addresses where the
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
--- /dev/null
+/*
+ * Copyright (C) Matrix Vision GmbH 2008
+ *
+ * Matrix Vision mvBlueLYNX-M7 configuration file
+ * based on Freescale's MPC8349ITX.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define MV_VERSION "v1.0.1"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1
+#define CONFIG_MPC83XX 1
+#define CONFIG_MPC834X 1
+#define CONFIG_MPC8343 1
+
+#define CFG_IMMR 0xE0000000
+
+#define CONFIG_PCI
+#define CONFIG_83XX_GENERIC_PCI
+#define CONFIG_PCI_SKIP_HOST_BRIDGE
+#define CONFIG_HARD_I2C
+#define CONFIG_TSEC_ENET
+#define CONFIG_MPC8XXX_SPI
+#define CONFIG_HARD_SPI
+#define MVBLM7_MMC_CS 0x04000000
+
+/* I2C */
+#undef CONFIG_SOFT_I2C
+
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_OFFSET 0x3000
+#define CFG_I2C2_OFFSET 0x3100
+
+#define CFG_I2C_SPEED 100000
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE 0x00000000
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+#define CFG_83XX_DDR_USES_CS0 1
+#define CFG_MEMTEST_START (60<<20)
+#define CFG_MEMTEST_END (70<<20)
+
+#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+
+#define CFG_DDR_SIZE 256
+
+/* HC, 75Ohm, DDR-II, DRQ */
+#define CFG_DDRCDR 0x80000001
+/* EN, ODT_WR, 3BA, 14row, 10col */
+#define CFG_DDR_CS0_CONFIG 0x80014102
+#define CFG_DDR_CS1_CONFIG 0x0
+#define CFG_DDR_CS2_CONFIG 0x0
+#define CFG_DDR_CS3_CONFIG 0x0
+
+#define CFG_DDR_CS0_BNDS 0x0000000f
+#define CFG_DDR_CS1_BNDS 0x0
+#define CFG_DDR_CS2_BNDS 0x0
+#define CFG_DDR_CS3_BNDS 0x0
+
+#define CFG_DDR_CLK_CNTL 0x02000000
+
+#define CFG_DDR_TIMING_0 0x00260802
+#define CFG_DDR_TIMING_1 0x2625b221
+#define CFG_DDR_TIMING_2 0x1f9820c7
+#define CFG_DDR_TIMING_3 0x00000000
+
+/* ~MEM_EN, SREN, DDR-II, 32_BE */
+#define CFG_DDR_SDRAM_CFG 0x43080000
+#define CFG_DDR_SDRAM_CFG2 0x00401000
+#define CFG_DDR_INTERVAL 0x04060100
+
+#define CFG_DDR_MODE 0x078e0232
+
+/* Flash */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+#define CFG_FLASH_BASE 0xFF800000
+#define CFG_FLASH_SIZE 8
+#define CFG_FLASH_SIZE_SHIFT 3
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_ERASE_TOUT 60000
+#define CFG_FLASH_WRITE_TOUT 500
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 256
+
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V)
+#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
+ OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
+ OR_GPCM_EAD)
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE
+#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
+
+/*
+ * U-Boot memory configuration
+ */
+#define CFG_MONITOR_BASE TEXT_BASE
+#undef CFG_RAMBOOT
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
+#define CFG_MONITOR_LEN (512 * 1024)
+#define CFG_MALLOC_LEN (512 * 1024)
+
+/*
+ * Local Bus LCRR and LBCR regs
+ * LCRR: DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CFG_LBC_LBCR 0x00000000
+
+/* LB sdram refresh timer, about 6us */
+#define CFG_LBC_LSRT 0x32000000
+/* LB refresh timer prescal, 266MHz/32*/
+#define CFG_LBC_MRTPR 0x20000000
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_CONSOLE ttyS0
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500)
+#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+#define MV_DTB_NAME "mvblm7.dtb"
+
+/*
+ * PCI
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x10000000
+#define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE)
+#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE 0x10000000
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xE2000000
+#define CFG_PCI1_IO_SIZE 0x01000000
+
+#define _IO_BASE 0x00000000
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 3
+
+#define PCI_66M
+#define CONFIG_83XX_CLKIN 66666667
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+
+/* TSEC */
+#define CONFIG_GMII
+#define CFG_VSC8601_SKEWFIX
+#define CFG_VSC8601_SKEW_TX 3
+#define CFG_VSC8601_SKEW_RX 3
+
+#define CONFIG_TSEC1
+#define CONFIG_TSEC2
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_FEC1_PHY_NORXERR
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
+#define TSEC1_PHY_ADDR 0x10
+#define TSEC1_PHYIDX 0
+#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
+
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define CONFIG_FEC2_PHY_NORXERR
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
+#define TSEC2_PHY_ADDR 0x11
+#define TSEC2_PHYIDX 0
+#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
+
+#define CONFIG_ETHPRIME "TSEC0"
+
+#define CONFIG_BOOTP_VENDOREX
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_RANDOM_DELAY
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+/* USB */
+#define CONFIG_HAS_FSL_DR_USB
+
+/*
+ * Environment
+ */
+#undef CFG_FLASH_PROTECTION
+#define CONFIG_ENV_OVERWRITE
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0xFF800000
+#define CFG_ENV_SIZE 0x2000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO
+#define CFG_LOADS_BAUD_CHANGE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_FPGA
+
+#undef CONFIG_WATCHDOG
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+/* default load address */
+#define CFG_LOAD_ADDR 0x2000000
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 0x200000
+
+#define CFG_PROMPT "mvBL-M7> "
+#define CFG_CBSIZE 256
+
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE CFG_CBSIZE
+#define CFG_HZ 1000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+#define CFG_HRCW_LOW 0x0
+#define CFG_HRCW_HIGH 0x0
+
+/*
+ * System performance
+ */
+#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
+#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
+#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
+#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
+
+/* clocking */
+#define CFG_SCCR_ENCCM 0
+#define CFG_SCCR_USBMPHCM 0
+#define CFG_SCCR_USBDRCM 2
+#define CFG_SCCR_TSEC1CM 1
+#define CFG_SCCR_TSEC2CM 1
+
+#define CFG_SICRH 0x1fff8003
+#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
+
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL CFG_HID0_INIT
+
+#define CFG_HID2 HID2_HBE
+
+/* DDR */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI */
+#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
+ BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* no PCI2 */
+#define CFG_IBAT3L 0
+#define CFG_IBAT3U 0
+#define CFG_IBAT4L 0
+#define CFG_IBAT4U 0
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
+#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT7L 0
+#define CFG_IBAT7U 0
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+#define CFG_DBAT4L CFG_IBAT4L
+#define CFG_DBAT4U CFG_IBAT4U
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV eth0
+
+/* Default path and filenames */
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR "s"
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_RESET_TO_RETRY 1000
+
+#define MV_CI "mvBL-M7"
+#define MV_VCI "mvBL-M7"
+#define MV_FPGA_DATA "0xfff80000"
+#define MV_FPGA_SIZE "0x76ca2"
+#define MV_KERNEL_ADDR "0xff810000"
+#define MV_INITRD_ADDR "0xffc00000"
+#define MV_AUTOSCR_ADDR "0xff804000"
+#define MV_AUTOSCR_ADDR2 "0xff806000"
+#define MV_DTB_ADDR "0xff808000"
+#define MV_INITRD_LENGTH "0x00300000"
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define MV_KERNEL_ADDR_RAM "0x00100000"
+#define MV_DTB_ADDR_RAM "0x00600000"
+#define MV_INITRD_ADDR_RAM "0x01000000"
+
+#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \
+ then autoscr ${autoscr_addr}; \
+ else autoscr ${autoscr_addr2}; \
+ fi;"
+#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console_nr=0\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0" \
+ "fpga=0\0" \
+ "fpgadata=" MV_FPGA_DATA "\0" \
+ "fpgadatasize=" MV_FPGA_SIZE "\0" \
+ "autoscr_addr=" MV_AUTOSCR_ADDR "\0" \
+ "autoscr_addr2=" MV_AUTOSCR_ADDR2 "\0" \
+ "mv_kernel_addr=" MV_KERNEL_ADDR "\0" \
+ "mv_kernel_addr_ram=" MV_KERNEL_ADDR_RAM "\0" \
+ "mv_initrd_addr=" MV_INITRD_ADDR "\0" \
+ "mv_initrd_addr_ram=" MV_INITRD_ADDR_RAM "\0" \
+ "mv_initrd_length=" MV_INITRD_LENGTH "\0" \
+ "mv_dtb_addr=" MV_DTB_ADDR "\0" \
+ "mv_dtb_addr_ram=" MV_DTB_ADDR_RAM "\0" \
+ "dtb_name=" MV_DTB_NAME "\0" \
+ "mv_version=" MV_VERSION "\0" \
+ "dhcp_client_id=" MV_CI "\0" \
+ "dhcp_vendor-class-identifier=" MV_VCI "\0" \
+ "netretry=no\0" \
+ "use_static_ipaddr=no\0" \
+ "static_ipaddr=192.168.90.10\0" \
+ "static_netmask=255.255.255.0\0" \
+ "static_gateway=0.0.0.0\0" \
+ "initrd_name=uInitrd.mvblm7-xenorfs\0" \
+ "zcip=no\0" \
+ "netboot=yes\0" \
+ "mvtest=Ff\0" \
+ "tried_bootfromflash=no\0" \
+ "tried_bootfromnet=no\0" \
+ "bootfile=mvblm72625.boot\0" \
+ "use_dhcp=yes\0" \
+ "gev_start=yes\0" \
+ "mvbcdma_debug=0\0" \
+ "mvbcia_debug=0\0" \
+ "propdev_debug=0\0" \
+ "gevss_debug=0\0" \
+ "watchdog=0\0" \
+ "usb_dr_mode=host\0" \
+ ""
+
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA CFG_ALTERA_CYCLON2
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+
+#endif
#define CSCONFIG_EN 0x80000000
#define CSCONFIG_AP 0x00800000
#define CSCONFIG_ODT_WR_ACS 0x00010000
+#define CSCONFIG_BANK_BIT_3 0x00004000
#define CSCONFIG_ROW_BIT 0x00000700
#define CSCONFIG_ROW_BIT_12 0x00000000
#define CSCONFIG_ROW_BIT_13 0x00000100
#ifndef USE_HOSTCC
#include <common.h>
+#else
+#include <string.h>
#endif /* USE_HOSTCC */
#include <watchdog.h>
#include <linux/types.h>
#ifndef USE_HOSTCC
#include <common.h>
+#else
+#include <string.h>
#endif /* USE_HOSTCC */
#include <watchdog.h>
#include <linux/string.h>
projects / platform / kernel / u-boot.git / commitdiff