Tablegen seg faulted when parsing a Pat where the destination part has
no output (zero instruction), due to a register class lookup using
nullptr.
Reviewed By: Paul-C-Anagnostopoulos
Differential Revision: https://reviews.llvm.org/D90829
--- /dev/null
+// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o /dev/null --warn-on-skipped-patterns 2>&1 < %s 2>&1 | FileCheck %s
+
+include "llvm/Target/Target.td"
+include "GlobalISelEmitterCommon.td"
+
+// CHECK: warning: Skipped pattern: Dst pattern root isn't a known leaf
+def : Pat<(zext (i16 (trunc i32:$src))),
+ (i32 $src)>;
if (Dst->isLeaf()) {
Record *RCDef = getInitValueAsRegClass(Dst->getLeafValue());
-
- const CodeGenRegisterClass &RC = Target.getRegisterClass(RCDef);
if (RCDef) {
+ const CodeGenRegisterClass &RC = Target.getRegisterClass(RCDef);
+
// We need to replace the def and all its uses with the specified
// operand. However, we must also insert COPY's wherever needed.
// For now, emit a copy and let the register allocator clean up.