[NFC] Clean-up typos in PowerPC CodeGen tests

diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
index e483b1823707cc5db8be43110537fd3e75ade190..6dea9ba934ec20f29b39a6cb5793bc797241d69c 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
@@ -1732,19 +1732,6 @@ define void @call_test_i1_stack() {
 ; ASM32PWR4-DAG:   li [[REGB]], 1
 ; ASM32PWR4-DAG:   bl .test_i1
 
-; ASM64PWR-DAG:    mflr 0
-; ASM64PWR-DAG:    li 3, 1
-; ASM64PWR-DAG:    li 4, 2
-; ASM64PWR-DAG:    li 5, 3
-; ASM64PWR-DAG:    li 6, 4
-; ASM64PWR-DAG:    li 7, 5
-; ASM64PWR-DAG:    li 8, 6
-; ASM64PWR-DAG:    li 9, 7
-; ASM64PWR-DAG:    li 10, 8
-; ASM64PWR-DAG:    std [[REGB:[0-9]+]], 112(1)
-; ASM64PWR-DAG:    li [[REGB]], 1
-; ASM64PWR-DAG:    bl .test_i1
-
 define double @test_fpr_stack(double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %s10, double %l11, double %d12, double %d13, float %f14, double %d15, float %f16) {
   entry:
     %add = fadd double %d1, %d2

diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
index b33ec0be95f8011d8a28fe8b57e46e21fa13b7f6..37c09cfa6408baaed4f8b71a040fd852b7991937 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
@@ -471,8 +471,6 @@ declare zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1)
 
 ; CHECK-LABEL: name: call_test_byval_5Byte{{.*}}
 
-; ASM-LABEL: .call_test_byval_5Byte:
-
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:  renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS5, $r2 :: (load (s32) from got)
@@ -780,7 +778,7 @@ entry:
 ; 64BIT-DAG:    STD killed renamable $x6, 24, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 24
 ; 64BIT-NEXT:   BLR8
 
-; ASM-LABEL: .test_byval_32Byte:
+; CHECKASM-LABEL: .test_byval_32Byte:
 
 ; ASM32:       stw 8, 44(1)
 ; ASM32:       stw 3, 24(1)

diff --git a/llvm/test/CodeGen/PowerPC/aix-csr.ll b/llvm/test/CodeGen/PowerPC/aix-csr.ll
index 7b89bdad9b0e2508da8cf3ed80af7f299afb1148..ec8ece74c50ebe0cf161be7e13249fe8886934a3 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-csr.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-csr.ll
@@ -83,7 +83,7 @@ entry:
 ; ASM64-DAG:      ld 16, -128(1)                  # 8-byte Folded Reload
 ; ASM64:          blr
 
-; ASM32-LABEl: .gprs_only:
+; ASM32-LABEL: .gprs_only:
 ; ASM32-DAG:     stw 16, -64(1)                  # 4-byte Folded Spill
 ; ASM32-DAG:     stw 22, -40(1)                  # 4-byte Folded Spill
 ; ASM32-DAG:     stw 30, -8(1)                   # 4-byte Folded Spill

diff --git a/llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll b/llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll
index 40b2fc2e08f1b3a9c53d481805e62f00dcd1285f..f124b0db5c648d759e5c15ca8d1fe5e96dc3b15d 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll
@@ -442,16 +442,6 @@ entry:
 ; shufflevector.  If halfword element 3 in BE mode(or 4 in LE mode) is the one
 ; we're attempting to insert, then we can use the vector insert instruction
 define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinserth 2, 2, 14
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_0_4:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI16_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI16_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_0_4:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C0(2)
@@ -471,16 +461,6 @@ entry:
 }
 
 define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI17_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_1_3:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinserth 2, 2, 2
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_1_3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinserth 2, 2, 2
@@ -496,16 +476,6 @@ entry:
 }
 
 define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI18_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI18_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_2_3:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinserth 2, 2, 4
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_2_3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinserth 2, 2, 4
@@ -521,16 +491,6 @@ entry:
 }
 
 define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinserth 2, 2, 8
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_3_4:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI19_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI19_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C1(2)
@@ -550,16 +510,6 @@ entry:
 }
 
 define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI20_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI20_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_4_3:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinserth 2, 2, 8
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_4_3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinserth 2, 2, 8
@@ -575,16 +525,6 @@ entry:
 }
 
 define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI21_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_5_3:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinserth 2, 2, 10
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_5_3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinserth 2, 2, 10
@@ -600,16 +540,6 @@ entry:
 }
 
 define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinserth 2, 2, 2
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_6_4:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI22_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI22_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C2(2)
@@ -629,16 +559,6 @@ entry:
 }
 
 define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinserth 2, 2, 0
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_7_4:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI23_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI23_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C3(2)
@@ -660,15 +580,6 @@ entry:
 ; The following testcases take one byte element from the second vector and
 ; inserts it at various locations in the first vector
 define <16 x i8> @shuffle_vector_byte_0_16(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-NEXT:    vinsertb 2, 3, 15
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_0_16:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 9
-; CHECK-BE-NEXT:    vinsertb 2, 3, 0
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_0_16:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 9
@@ -686,15 +597,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_1_25(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 15
-; CHECK-NEXT:    vinsertb 2, 3, 14
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_1_25:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-BE-NEXT:    vinsertb 2, 3, 1
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_1_25:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 2
@@ -712,15 +614,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_2_18(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-NEXT:    vinsertb 2, 3, 13
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_2_18:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 11
-; CHECK-BE-NEXT:    vinsertb 2, 3, 2
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_2_18:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 11
@@ -738,15 +631,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_3_27(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 13
-; CHECK-NEXT:    vinsertb 2, 3, 12
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_3_27:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-BE-NEXT:    vinsertb 2, 3, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_3_27:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 4
@@ -764,15 +648,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_4_20(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-NEXT:    vinsertb 2, 3, 11
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_4_20:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 13
-; CHECK-BE-NEXT:    vinsertb 2, 3, 4
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_4_20:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 13
@@ -790,15 +665,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_5_29(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 11
-; CHECK-NEXT:    vinsertb 2, 3, 10
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_5_29:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-BE-NEXT:    vinsertb 2, 3, 5
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_5_29:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 6
@@ -816,15 +682,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_6_22(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-NEXT:    vinsertb 2, 3, 9
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_6_22:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 15
-; CHECK-BE-NEXT:    vinsertb 2, 3, 6
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_6_22:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 15
@@ -842,15 +699,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_7_31(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 9
-; CHECK-NEXT:    vinsertb 2, 3, 8
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_7_31:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-BE-NEXT:    vinsertb 2, 3, 7
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_7_31:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 8
@@ -868,14 +716,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_8_24(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 3, 7
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_8_24:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 1
-; CHECK-BE-NEXT:    vinsertb 2, 3, 8
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_8_24:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 1
@@ -893,15 +733,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_9_17(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 7
-; CHECK-NEXT:    vinsertb 2, 3, 6
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_9_17:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-BE-NEXT:    vinsertb 2, 3, 9
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_9_17:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 10
@@ -919,15 +750,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_10_26(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-NEXT:    vinsertb 2, 3, 5
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_10_26:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 3
-; CHECK-BE-NEXT:    vinsertb 2, 3, 10
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_10_26:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 3
@@ -945,15 +767,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_11_19(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 5
-; CHECK-NEXT:    vinsertb 2, 3, 4
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_11_19:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-BE-NEXT:    vinsertb 2, 3, 11
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_11_19:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 12
@@ -971,15 +784,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_12_28(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-NEXT:    vinsertb 2, 3, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_12_28:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 5
-; CHECK-BE-NEXT:    vinsertb 2, 3, 12
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_12_28:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 5
@@ -997,15 +801,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_13_21(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 3
-; CHECK-NEXT:    vinsertb 2, 3, 2
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_13_21:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-BE-NEXT:    vinsertb 2, 3, 13
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_13_21:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 14
@@ -1023,15 +818,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_14_30(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-NEXT:    vinsertb 2, 3, 1
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_14_30:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 7
-; CHECK-BE-NEXT:    vinsertb 2, 3, 14
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_14_30:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 7
@@ -1049,14 +835,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_15_23(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 1
-; CHECK-NEXT:    vinsertb 2, 3, 0
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_15_23:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 3, 15
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_15_23:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 3, 15
@@ -1665,16 +1443,6 @@ entry:
 ; shufflevector.  If byte element 7 in BE mode(or 8 in LE mode) is the one
 ; we're attempting to insert, then we can use the vector insert instruction
 define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI56_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI56_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_0_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 0
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_0_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 0
@@ -1690,16 +1458,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 14
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_1_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI57_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI57_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_1_8:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C4(2)
@@ -1719,16 +1477,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 13
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_2_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI58_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI58_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_2_8:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C5(2)
@@ -1748,16 +1496,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI59_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI59_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_3_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_3_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 3
@@ -1773,16 +1511,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI60_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI60_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_4_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 4
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_4_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 4
@@ -1798,16 +1526,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 10
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_5_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI61_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI61_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_5_8:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C6(2)
@@ -1827,16 +1545,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 9
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_6_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI62_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI62_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_6_8:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C7(2)
@@ -1856,16 +1564,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 8
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_7_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI63_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI63_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_7_8:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C8(2)
@@ -1885,16 +1583,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI64_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI64_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_8_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 8
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_8_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 8
@@ -1910,16 +1598,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI65_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI65_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_9_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 9
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_9_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 9
@@ -1935,16 +1613,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI66_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI66_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_10_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 10
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_10_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 10
@@ -1960,16 +1628,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 4
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_11_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI67_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI67_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_11_8:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C9(2)
@@ -1989,16 +1647,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_12_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI68_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI68_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_12_8:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C10(2)
@@ -2018,16 +1666,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI69_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI69_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_13_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 13
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_13_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 13
@@ -2043,16 +1681,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI70_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI70_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_14_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 14
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_14_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 14
@@ -2068,16 +1696,6 @@ entry:
 }
 
 define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 0
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_15_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI71_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI71_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_15_8:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 3, L..C11(2)

diff --git a/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll b/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
index 7c79796880e6b92eefee319d10bd97e794519e7c..afe4ce3ab6db791341b42f71dd698d42d0b60db2 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
+++ b/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
@@ -24,7 +24,7 @@ entry:
 ; CHECK:          STD killed renamable $x3, 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0, align 16)
 ; CHECK-NEXT:     renamable $x3 = LBZ8 4, %fixed-stack.0 :: (dereferenceable load (s8)
 
-; CHECKASM-LABEL: .test_byval_5Byte:
+; ASM-LABEL: .test_byval_5Byte:
 
 ; ASM:       std 3, 48(1)
 ; ASM-NEXT:  lbz 3, 52(1)
@@ -49,7 +49,7 @@ entry:
 ; CHECK:          STD killed renamable $x3, 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0, align 16)
 ; CHECK-NEXT:     renamable $x3 = LBZ8 5, %fixed-stack.0 :: (dereferenceable load (s8)
 
-; CHECKASM-LABEL: .test_byval_6Byte:
+; ASM-LABEL: .test_byval_6Byte:
 
 ; ASM:       std 3, 48(1)
 ; ASM-NEXT:  lbz 3, 53(1)
@@ -74,7 +74,7 @@ entry:
 ; CHECK:          STD killed renamable $x3, 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0, align 16)
 ; CHECK-NEXT:     renamable $x3 = LBZ8 6, %fixed-stack.0 :: (dereferenceable load (s8)
 
-; CHECKASM-LABEL: .test_byval_7Byte:
+; ASM-LABEL: .test_byval_7Byte:
 
 ; ASM:       std 3, 48(1)
 ; ASM-NEXT:  lbz 3, 54(1)
@@ -101,7 +101,7 @@ entry:
 ; CHECK-DAG:      STD killed renamable $x[[SCRATCH]], 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0, align 16)
 
 
-; CHECKASM-LABEL: .test_byval_8Byte:
+; ASM-LABEL: .test_byval_8Byte:
 
 ; ASM:       mr [[SCRATCH:[0-9]+]], 3
 ; ASM-DAG:   clrldi  3, 3, 56
@@ -137,7 +137,7 @@ declare void @test_byval_64Byte(%struct.S64* byval(%struct.S64) align 1)
 ; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_64Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
 ; CHECK-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
-; CHECKASM-LABEL: .test_byval_64Byte:
+; ASM-LABEL: .call_test_byval_64Byte:
 
 ; ASM:         stdu 1, -112(1)
 ; ASM-NEXT:    ld [[REG:[0-9]+]], L..C{{[0-9]+}}(2)

diff --git a/llvm/test/CodeGen/PowerPC/atomics-indexed.ll b/llvm/test/CodeGen/PowerPC/atomics-indexed.ll
index cf7225a5fc200517e86e54dddcc8c6c9c6125244..eaebf305e5cb252e0bdbf4eacfb6bf1fa3fe992b 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/atomics-indexed.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-indexed.ll
@@ -28,10 +28,6 @@ define i8 @load_x_i8_seq_cst([100000 x i8]* %mem) {
 ; PPC64-NEXT:    bne- cr7, .+4
 ; PPC64-NEXT:    isync
 ; PPC64-NEXT:    blr
-; CHECK-PPC32: lwsync
-; CHECK-PPC64: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
-; CHECK-PPC64: bne- [[CR]], .+4
-; CHECK-PPC64: isync
   %ptr = getelementptr inbounds [100000 x i8], [100000 x i8]* %mem, i64 0, i64 90000
   %val = load atomic i8, i8* %ptr seq_cst, align 1
   ret i8 %val
@@ -54,10 +50,6 @@ define i16 @load_x_i16_acquire([100000 x i16]* %mem) {
 ; PPC64-NEXT:    bne- cr7, .+4
 ; PPC64-NEXT:    isync
 ; PPC64-NEXT:    blr
-; CHECK-PPC32: lwsync
-; CHECK-PPC64: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
-; CHECK-PPC64: bne- [[CR]], .+4
-; CHECK-PPC64: isync
   %ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000
   %val = load atomic i16, i16* %ptr acquire, align 2
   ret i16 %val

diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
index 5bc5bceb5eeb226cd83060391cb27626c23e0829..417b65752340b5ebdcf36cf0856e5c34a19efc66 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
@@ -28,10 +28,6 @@ define dso_local void @test_stfiw(i32* %cia, double %da) {
 ; CHECK-32BIT:       # %bb.0: # %entry
 ; CHECK-32BIT-NEXT:    stfiwx 1, 0, 3
 ; CHECK-32BIT-NEXT:    blr
-; CHECK-PWR9-LABEL: test_stfiw:
-; CHECK-PWR9:       # %bb.0: # %entry
-; CHECK-PWR9-NEXT:    stxsiwx 1, 0, 3
-; CHECK-PWR9-NEXT:    blr
 entry:
   %0 = bitcast i32* %cia to i8*
   tail call void @llvm.ppc.stfiw(i8* %0, double %da)
@@ -53,10 +49,6 @@ define dso_local void @test_xl_stfiw(i32* %cia, double %da) {
 ; CHECK-32BIT:       # %bb.0: # %entry
 ; CHECK-32BIT-NEXT:    stfiwx 1, 0, 3
 ; CHECK-32BIT-NEXT:    blr
-; CHECK-PWR9-LABEL: test_xl_stfiw:
-; CHECK-PWR9:       # %bb.0: # %entry
-; CHECK-PWR9-NEXT:    stxsiwx 1, 0, 3
-; CHECK-PWR9-NEXT:    blr
 entry:
   %0 = bitcast i32* %cia to i8*
   tail call void @llvm.ppc.stfiw(i8* %0, double %da)

diff --git a/llvm/test/CodeGen/PowerPC/complex-return.ll b/llvm/test/CodeGen/PowerPC/complex-return.ll
index b25420a48e6923b317c2b75f82ef3dc76b148a89..74fd3cb0535e579088edfa89a5de16fdcbe0669c 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/complex-return.ll
+++ b/llvm/test/CodeGen/PowerPC/complex-return.ll
@@ -27,7 +27,7 @@ entry:
 ; CHECK-DAG: lfd 1
 ; CHECK-DAG: lfd 2
 ; CHECK-DAG: lfd 3
-; CHECK_DAG: lfd 4
+; CHECK-DAG: lfd 4
 
 define { float, float } @oof() nounwind {
 entry:

diff --git a/llvm/test/CodeGen/PowerPC/duplicate-returns-for-tailcall.ll b/llvm/test/CodeGen/PowerPC/duplicate-returns-for-tailcall.ll
index 9c0e77dafde637daa7faa29b0cbccf3b99aae2f9..ee67d55f82fe61f4cce9ace403f97b5dd3b0c4e2 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/duplicate-returns-for-tailcall.ll
+++ b/llvm/test/CodeGen/PowerPC/duplicate-returns-for-tailcall.ll
@@ -43,7 +43,7 @@ if.then6:                                         ; preds = %if.end4
   %call7 = tail call fastcc signext i32 @call3(i32 signext %a, i32 signext %b, i32 signext %c)
   br label %return
 ; tail calling a fastcc function from a ccc function is supported.
-; CHECK_LABEL: if.then13:
+; CHECK-LABEL: if.then6:
 ; CHECK:       %[[T2:[a-zA-Z0-9]+]] = tail call fastcc signext i32 @call3
 ; CHECK-NEXT:  ret i32 %[[T2]]
 

diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll b/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll
index ca34aad7ee186f534603b9bf2eac23d9dffab9cd..2233c5bac5233e1bb6d93941c5db57b5c6f843f3 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll
@@ -267,7 +267,6 @@ entry:
 ; CHECK-NEXT: li
 ; CHECK-NEXT: lfiwzx
 ; CHECK-NEXT: fcfidu
-; CHECKLE: fcfidu
 ; PPC970-NOT: lfiwzx
 ; PPC970-NOT: fcfidu
 ; SPE: efdcfui

diff --git a/llvm/test/CodeGen/PowerPC/float-to-int.ll b/llvm/test/CodeGen/PowerPC/float-to-int.ll
index 54f9cecbc8fed1fff7d814a5f2ae0310b4938a7c..c36f354449fde7a488d954d9cf3ee88f578ac57f 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/float-to-int.ll
+++ b/llvm/test/CodeGen/PowerPC/float-to-int.ll
@@ -25,7 +25,7 @@ define i64 @foo(float %a) nounwind {
 ; CHECK-VSX: ld 3,
 ; CHECK-VSX: blr
 
-; CHECK-LABEL-P9: @foo
+; CHECK-P9-LABEL: @foo
 ; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 1
 ; CHECK-P9: stfd [[REG]],
 ; CHECK-P9: ld 3,
@@ -48,7 +48,7 @@ define i64 @foo2(double %a) nounwind {
 ; CHECK-VSX: ld 3,
 ; CHECK-VSX: blr
 
-; CHECK-LABEL-P9: @foo2
+; CHECK-P9-LABEL: @foo2
 ; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 1
 ; CHECK-P9: stfd [[REG]],
 ; CHECK-P9: ld 3,
@@ -71,7 +71,7 @@ define i64 @foo3(float %a) nounwind {
 ; CHECK-VSX: ld 3,
 ; CHECK-VSX: blr
 
-; CHECK-LABEL-P9: @foo3
+; CHECK-P9-LABEL: @foo3
 ; CHECK-P9: xscvdpuxds [[REG:[0-9]+]], 1
 ; CHECK-P9: stfd [[REG]],
 ; CHECK-P9: ld 3,
@@ -94,7 +94,7 @@ define i64 @foo4(double %a) nounwind {
 ; CHECK-VSX: ld 3,
 ; CHECK-VSX: blr
 
-; CHECK-LABEL-P9: @foo4
+; CHECK-P9-LABEL: @foo4
 ; CHECK-P9: xscvdpuxds [[REG:[0-9]+]], 1
 ; CHECK-P9: stfd [[REG]],
 ; CHECK-P9: ld 3,

diff --git a/llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll b/llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
index d5f9852169c7a20baba0619abc44af617957b0ad..c326ec5bd66eb4ae5e785d79d54c8f561439ed13 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
@@ -7,15 +7,6 @@
 ; RUN:   FileCheck %s --check-prefix=CHECK-AIX32
 
 define dso_local void @mtfsb0() local_unnamed_addr #0 {
-; CHECK-PWR8-LABEL: mtfsb0:
-; CHECK-PWR8:       # %bb.0: # %entry
-; CHECK-PWR8-NEXT:    mtfsb0 10
-; CHECK-PWR8-NEXT:    blr
-;
-; CHECK-PWR7-LABEL: mtfsb0:
-; CHECK-PWR7:       # %bb.0: # %entry
-; CHECK-PWR7-NEXT:    mtfsb0 10
-; CHECK-PWR7-NEXT:    blr
 ; CHECK-LABEL: mtfsb0:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mtfsb0 10
@@ -36,15 +27,6 @@ entry:
 }
 
 define dso_local void @mtfsb1() local_unnamed_addr #0 {
-; CHECK-PWR8-LABEL: mtfsb1:
-; CHECK-PWR8:       # %bb.0: # %entry
-; CHECK-PWR8-NEXT:    mtfsb1 0
-; CHECK-PWR8-NEXT:    blr
-;
-; CHECK-PWR7-LABEL: mtfsb1:
-; CHECK-PWR7:       # %bb.0: # %entry
-; CHECK-PWR7-NEXT:    mtfsb1 0
-; CHECK-PWR7-NEXT:    blr
 ; CHECK-LABEL: mtfsb1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mtfsb1 0

diff --git a/llvm/test/CodeGen/PowerPC/jaggedstructs.ll b/llvm/test/CodeGen/PowerPC/jaggedstructs.ll
index f897f4a5eee3616f5fd9ca7b7c8d4ec03da4b39b..f8098dda3a8a66d67e12192f7f4e45ce99cdf296 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/jaggedstructs.ll
+++ b/llvm/test/CodeGen/PowerPC/jaggedstructs.ll
@@ -36,7 +36,7 @@ entry:
 ; CHECK-DAG: lbz {{[0-9]+}}, 167(1)
 ; CHECK-DAG: lhz {{[0-9]+}}, 165(1)
 ; CHECK-DAG: stb {{[0-9]+}}, 55(1)
-; CHECK-DAG-DAG: sth {{[0-9]+}}, 53(1)
+; CHECK-DAG: sth {{[0-9]+}}, 53(1)
 ; CHECK-DAG: lbz {{[0-9]+}}, 175(1)
 ; CHECK-DAG: lwz {{[0-9]+}}, 171(1)
 ; CHECK-DAG: stb {{[0-9]+}}, 63(1)

diff --git a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
index 27ee2fda1f1b031f0e6271c2430c2039c462c9dd..38ce3708f700635b5409fba90eb46751bb06aa9f 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
+++ b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
@@ -2496,7 +2496,6 @@ entry:
   ret double %vecext
 
 
-; CHECK-AIXT: xxlor 1, 34, 34
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -2520,8 +2519,6 @@ define double @getd1(<2 x double> %vd) {
 entry:
   %vecext = extractelement <2 x double> %vd, i32 1
   ret double %vecext
-
-
 }
 
 ; Function Attrs: norecurse nounwind readnone

diff --git a/llvm/test/CodeGen/PowerPC/ppc-passname.ll b/llvm/test/CodeGen/PowerPC/ppc-passname.ll
index 06f13278d84cd39f66c9a5b91e106154f3cca941..8f430e4e0ba3356f86a25fbbb4844fb9f1602703 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/ppc-passname.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc-passname.ll
@@ -42,7 +42,7 @@
 
 ; RUN: llc -mtriple=powerpc64le-unknown-unknown < %s -debug-pass=Structure -stop-after=ppc-early-ret -o /dev/null 2>&1 | FileCheck %s -check-prefix=STOP-AFTER-EARLY-RET
 ; STOP-AFTER-EARLY-RET: -ppc-early-ret
-; STOP-AFTER-ERALY-RET-NOT: "ppc-early-ret" pass is not registered.
+; STOP-AFTER-EARLY-RET-NOT: "ppc-early-ret" pass is not registered.
 ; STOP-AFTER-EARLY-RET: PowerPC Early-Return Creation
 
 

diff --git a/llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll b/llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll
index 856b66d4e7a19401caad0e11f5932f567c18f757..1c083c38dc12d1f62439225728ccd557ba2f749e 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll
@@ -28,12 +28,6 @@ exit:
     i32 %bf.load)
   ret i8 %call.i
 
-; CHECK-SCO-SHRK-LABEL: _ZNK5clang9NamedDecl23getLinkageAndVisibilityEv:
-; CHECK-SCO-SHRK: b LVComputationKind
-; CHECK-SCO-SHRK: #TC_RETURNd8
-; CHECK-SCO-SHRK: stdu 1, -{{[0-9]+}}(1)
-; CHECK-SCO-SHRK: bl __assert_fail
-;
 ; CHECK-SCO-ONLY-LABEL: _ZNK5clang9NamedDecl23getLinkageAndVisibilityEv:
 ; CHECK-SCO-ONLY: stdu 1, -{{[0-9]+}}(1)
 ; CHECK-SCO-ONLY: b LVComputationKind

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll b/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
index 25586b97770fa0c58cc112c0a4ba27c25c170876..5e9be76af7a84a8874704669f87dd8fa6892f414 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
@@ -76,7 +76,6 @@ entry:
   %conv3 = zext i1 %cmp to i8
   store i8 %conv3, i8* @glob
   ret void
-; CHECK_LABEL: test_igeuc_store:
 }
 
 ; Function Attrs: norecurse nounwind

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeui.ll b/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
index 3b5fed0c85b5ec7db8fc936a031295c0bf26ad37..d6b53c0a347740abd8f2226d274eaf1c9e395e3a 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
@@ -75,7 +75,6 @@ entry:
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @glob
   ret void
-; CHECK_LABEL: test_igeuc_store:
 }
 
 ; Function Attrs: norecurse nounwind

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeus.ll b/llvm/test/CodeGen/PowerPC/testComparesigeus.ll
index 05bf4bf5c82012a9884c1704e2866938f9c9dfc6..b8a0a1764c74bd2241f7c9d6b28686bbef5a34f8 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesigeus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeus.ll
@@ -75,7 +75,6 @@ entry:
   %conv3 = zext i1 %cmp to i16
   store i16 %conv3, i16* @glob
   ret void
-; CHECK_LABEL: test_igeus_store:
 }
 
 ; Function Attrs: norecurse nounwind

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll b/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll
index 0f5aa673282ab3bddeb00d590bcb61d73121e123..aa3c6ba797df08a2f7de18f17ae6f39a520b4dd7 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll
@@ -83,7 +83,6 @@ define void @test_igtsll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
 entry:
   %cmp = icmp sgt i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -105,7 +104,6 @@ define void @test_igtsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
 entry:
   %cmp = icmp sgt i64 %a, %b
   %conv1 = sext i1 %cmp to i64

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll b/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
index 252517c900bf1f019441707604170cfd01e630b9..52c256912555dba553d998c84400d06b374e71f0 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
@@ -65,7 +65,6 @@ define dso_local void @test_iltsll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
 entry:
   %cmp = icmp slt i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -86,7 +85,6 @@ define dso_local void @test_iltsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
 entry:
   %cmp = icmp slt i64 %a, %b
   %conv1 = sext i1 %cmp to i64

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
index b6c906670703fe4300b6911603c4b2f47087b888..92e91d78b8c2cb7e8985a51d9bedd833ab7b2452 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
@@ -75,7 +75,6 @@ entry:
   %conv3 = zext i1 %cmp to i8
   store i8 %conv3, i8* @glob
   ret void
-; CHECK_LABEL: test_llgeuc_store:
 }
 
 ; Function Attrs: norecurse nounwind

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
index ebb3434cbc9bff4781a5895023df9a55183077fb..f75b5f89a6cdd8996326bf884b437d6262e2ad03 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
@@ -75,7 +75,6 @@ entry:
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @glob
   ret void
-; CHECK_LABEL: test_igeuc_store:
 }
 
 ; Function Attrs: norecurse nounwind

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
index 383876c7e1e46a9aa95d39722ff36c105e2832b0..8c41f1d7ec2d0b7fb25dcb6efc4865574ddbfcb2 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
@@ -75,7 +75,6 @@ entry:
   %conv3 = zext i1 %cmp to i16
   store i16 %conv3, i16* @glob
   ret void
-; CHECK_LABEL: test_llgeus_store:
 }
 
 ; Function Attrs: norecurse nounwind

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll
index ae7c15e00cee1ddca55e7d20655f5fee24d1ffeb..f7dff13de8e81f7eb64fec2a0c3bb4b4999dadd3 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll
@@ -83,7 +83,6 @@ define void @test_llgtsll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
 entry:
   %cmp = icmp sgt i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -105,7 +104,6 @@ define void @test_llgtsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
 entry:
   %cmp = icmp sgt i64 %a, %b
   %conv1 = sext i1 %cmp to i64

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll b/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
index 423047a1ad04a526ca7ce6251948f95648eb8ebf..7af71b3cf85af55ec2187e01fb4be396d34d504b 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
@@ -65,7 +65,6 @@ define dso_local void @test_llltsll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
 entry:
   %cmp = icmp slt i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -86,7 +85,6 @@ define dso_local void @test_llltsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
 entry:
   %cmp = icmp slt i64 %a, %b
   %conv1 = sext i1 %cmp to i64

diff --git a/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll b/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
index 247961e85b1215a20393476abc668cd653c70604..b149c74e44ba213f7b04a152d851640fd5925a61 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
+++ b/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
@@ -35,7 +35,7 @@ entry:
 ; CHECK-BE-DAG: sldi [[SHAMREG:[0-9]+]], [[ANDCREG]], 5
 ; CHECK-BE: mfvsrd [[TOGPR:[0-9]+]],
 ; CHECK-BE: srd [[RSHREG:[0-9]+]], [[TOGPR]], [[SHAMREG]]
-; CHECk-BE: extsw 3, [[RSHREG]]
+; CHECK-BE: extsw 3, [[RSHREG]]
 }
 
 ; Function Attrs: norecurse nounwind readnone

diff --git a/llvm/test/CodeGen/PowerPC/vec_xxpermdi.ll b/llvm/test/CodeGen/PowerPC/vec_xxpermdi.ll
index 9be2a1864a04ef8bddc8e08ee8145d2608f73bb3..b2b019127cefea9be4f0fd5922c4ab3252b02599 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/vec_xxpermdi.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_xxpermdi.ll
@@ -159,7 +159,7 @@ define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_2(<2 x double> %VA) {
       %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 0>
       ret <2 x double> %0
 ; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_2
-; CHCECK-LE: xxswapd 34, 34
+; CHECK-LE: xxswapd 34, 34
 }
 
 define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_3(<2 x double> %VA) {
@@ -266,7 +266,7 @@ define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_2(<2 x double> %VA) {
       %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 0>
       ret <2 x double> %0
 ; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_2
-; CHCECK-LE: xxswapd 34, 34
+; CHECK-LE: xxswapd 34, 34
 }
 
 define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_3(<2 x double> %VA) {

diff --git a/llvm/test/CodeGen/PowerPC/vrsave-inline-asm.ll b/llvm/test/CodeGen/PowerPC/vrsave-inline-asm.ll
index 32dd513bd0689f571d08840736a936d5548f645c..c50b17e31c5070b43753deb4bb6a4dff75c41cd3 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/vrsave-inline-asm.ll
+++ b/llvm/test/CodeGen/PowerPC/vrsave-inline-asm.ll
@@ -29,7 +29,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK-LABEl: moveToVRSave:
+; CHECK-LABEL: moveToVRSave:
 ; CHECK:         mtvrsave 3
 
 ; CHECK-LABEL: moveFromVRSave: