RDMA/hns: Fix wrong timer context buffer page size

The HEM page size for QPC timer and CQC timer is always 4K and there's no
need to calculate a different size by the hns driver, otherwise the ROCEE
may access an invalid address.

Fixes: 719d13415f59 ("RDMA/hns: Remove duplicated hem page size config code")
Link: https://lore.kernel.org/r/1621589395-2435-4-git-send-email-liweihang@huawei.com
Signed-off-by: Xi Wang <wangxi11@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>

diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index 0c12d87..17cf51a 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -2057,12 +2057,6 @@ static void set_hem_page_size(struct hns_roce_dev *hr_dev)
        calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num,
                   1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
 
-       if (caps->cqc_timer_entry_sz)
-               calc_pg_sz(caps->num_cqc_timer, caps->cqc_timer_entry_sz,
-                          caps->cqc_timer_hop_num, caps->cqc_timer_bt_num,
-                          &caps->cqc_timer_buf_pg_sz,
-                          &caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER);
-
        /* SRQ */
        if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) {
                caps->srqc_ba_pg_sz = 0;