Value name propagation improved.
define <4 x float> @mload_v4f32_cmp(ptr %f, <4 x i32> %src) {
; CHECK-LABEL: @mload_v4f32_cmp(
; CHECK-NEXT: [[ICMP:%.*]] = icmp ne <4 x i32> [[SRC:%.*]], zeroinitializer
-; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0(ptr [[F:%.*]], i32 1, <4 x i1> [[ICMP]], <4 x float> zeroinitializer)
-; CHECK-NEXT: ret <4 x float> [[TMP1]]
+; CHECK-NEXT: [[LD:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0(ptr [[F:%.*]], i32 1, <4 x i1> [[ICMP]], <4 x float> zeroinitializer)
+; CHECK-NEXT: ret <4 x float> [[LD]]
;
%icmp = icmp ne <4 x i32> %src, zeroinitializer
%mask = sext <4 x i1> %icmp to <4 x i32>
define <4 x float> @mload_one_one(ptr %f) {
; CHECK-LABEL: @mload_one_one(
-; CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0(ptr [[F:%.*]], i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float poison>)
-; CHECK-NEXT: ret <4 x float> [[TMP1]]
+; CHECK-NEXT: [[LD:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0(ptr [[F:%.*]], i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float poison>)
+; CHECK-NEXT: ret <4 x float> [[LD]]
;
%ld = tail call <4 x float> @llvm.x86.avx.maskload.ps(ptr %f, <4 x i32> <i32 0, i32 0, i32 0, i32 -1>)
ret <4 x float> %ld
define <2 x double> @mload_one_one_double(ptr %f) {
; CHECK-LABEL: @mload_one_one_double(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0(ptr [[F:%.*]], i32 1, <2 x i1> <i1 true, i1 false>, <2 x double> <double poison, double 0.000000e+00>)
-; CHECK-NEXT: ret <2 x double> [[TMP1]]
+; CHECK-NEXT: [[LD:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0(ptr [[F:%.*]], i32 1, <2 x i1> <i1 true, i1 false>, <2 x double> <double poison, double 0.000000e+00>)
+; CHECK-NEXT: ret <2 x double> [[LD]]
;
%ld = tail call <2 x double> @llvm.x86.avx.maskload.pd(ptr %f, <2 x i64> <i64 -1, i64 0>)
ret <2 x double> %ld
define <8 x float> @mload_v8f32(ptr %f) {
; CHECK-LABEL: @mload_v8f32(
-; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.masked.load.v8f32.p0(ptr [[F:%.*]], i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>)
-; CHECK-NEXT: ret <8 x float> [[TMP1]]
+; CHECK-NEXT: [[LD:%.*]] = call <8 x float> @llvm.masked.load.v8f32.p0(ptr [[F:%.*]], i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>)
+; CHECK-NEXT: ret <8 x float> [[LD]]
;
%ld = tail call <8 x float> @llvm.x86.avx.maskload.ps.256(ptr %f, <8 x i32> <i32 0, i32 0, i32 0, i32 -1, i32 0, i32 0, i32 0, i32 0>)
ret <8 x float> %ld
; CHECK-NEXT: [[ICMP0:%.*]] = fcmp one <8 x float> [[SRC0:%.*]], zeroinitializer
; CHECK-NEXT: [[ICMP1:%.*]] = fcmp one <8 x float> [[SRC1:%.*]], zeroinitializer
; CHECK-NEXT: [[MASK1:%.*]] = and <8 x i1> [[ICMP0]], [[ICMP1]]
-; CHECK-NEXT: [[TMP1:%.*]] = call <8 x float> @llvm.masked.load.v8f32.p0(ptr [[F:%.*]], i32 1, <8 x i1> [[MASK1]], <8 x float> zeroinitializer)
-; CHECK-NEXT: ret <8 x float> [[TMP1]]
+; CHECK-NEXT: [[LD:%.*]] = call <8 x float> @llvm.masked.load.v8f32.p0(ptr [[F:%.*]], i32 1, <8 x i1> [[MASK1]], <8 x float> zeroinitializer)
+; CHECK-NEXT: ret <8 x float> [[LD]]
;
%icmp0 = fcmp one <8 x float> %src0, zeroinitializer
%icmp1 = fcmp one <8 x float> %src1, zeroinitializer
define <4 x double> @mload_v4f64(ptr %f) {
; CHECK-LABEL: @mload_v4f64(
-; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr [[F:%.*]], i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> <double poison, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>)
-; CHECK-NEXT: ret <4 x double> [[TMP1]]
+; CHECK-NEXT: [[LD:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr [[F:%.*]], i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> <double poison, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>)
+; CHECK-NEXT: ret <4 x double> [[LD]]
;
%ld = tail call <4 x double> @llvm.x86.avx.maskload.pd.256(ptr %f, <4 x i64> <i64 -1, i64 0, i64 0, i64 0>)
ret <4 x double> %ld
define <4 x i32> @mload_v4i32(ptr %f) {
; CHECK-LABEL: @mload_v4i32(
-; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[F:%.*]], i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x i32> <i32 0, i32 0, i32 0, i32 poison>)
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[LD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[F:%.*]], i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x i32> <i32 0, i32 0, i32 0, i32 poison>)
+; CHECK-NEXT: ret <4 x i32> [[LD]]
;
%ld = tail call <4 x i32> @llvm.x86.avx2.maskload.d(ptr %f, <4 x i32> <i32 0, i32 0, i32 0, i32 -1>)
ret <4 x i32> %ld
define <2 x i64> @mload_v2i64(ptr %f) {
; CHECK-LABEL: @mload_v2i64(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.masked.load.v2i64.p0(ptr [[F:%.*]], i32 1, <2 x i1> <i1 true, i1 false>, <2 x i64> <i64 poison, i64 0>)
-; CHECK-NEXT: ret <2 x i64> [[TMP1]]
+; CHECK-NEXT: [[LD:%.*]] = call <2 x i64> @llvm.masked.load.v2i64.p0(ptr [[F:%.*]], i32 1, <2 x i1> <i1 true, i1 false>, <2 x i64> <i64 poison, i64 0>)
+; CHECK-NEXT: ret <2 x i64> [[LD]]
;
%ld = tail call <2 x i64> @llvm.x86.avx2.maskload.q(ptr %f, <2 x i64> <i64 -1, i64 0>)
ret <2 x i64> %ld
define <8 x i32> @mload_v8i32(ptr %f) {
; CHECK-LABEL: @mload_v8i32(
-; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0(ptr [[F:%.*]], i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i32> <i32 0, i32 0, i32 0, i32 poison, i32 0, i32 0, i32 0, i32 0>)
-; CHECK-NEXT: ret <8 x i32> [[TMP1]]
+; CHECK-NEXT: [[LD:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0(ptr [[F:%.*]], i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i32> <i32 0, i32 0, i32 0, i32 poison, i32 0, i32 0, i32 0, i32 0>)
+; CHECK-NEXT: ret <8 x i32> [[LD]]
;
%ld = tail call <8 x i32> @llvm.x86.avx2.maskload.d.256(ptr %f, <8 x i32> <i32 0, i32 0, i32 0, i32 -1, i32 0, i32 0, i32 0, i32 0>)
ret <8 x i32> %ld
define <4 x i64> @mload_v4i64(ptr %f) {
; CHECK-LABEL: @mload_v4i64(
-; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr [[F:%.*]], i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> <i64 poison, i64 0, i64 0, i64 0>)
-; CHECK-NEXT: ret <4 x i64> [[TMP1]]
+; CHECK-NEXT: [[LD:%.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr [[F:%.*]], i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> <i64 poison, i64 0, i64 0, i64 0>)
+; CHECK-NEXT: ret <4 x i64> [[LD]]
;
%ld = tail call <4 x i64> @llvm.x86.avx2.maskload.q.256(ptr %f, <4 x i64> <i64 -1, i64 0, i64 0, i64 0>)
ret <4 x i64> %ld
define i1 @test23(i32 %A) {
; CHECK-LABEL: @test23(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[A:%.*]], 2
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[D:%.*]] = icmp eq i32 [[A:%.*]], 2
+; CHECK-NEXT: ret i1 [[D]]
;
%B = icmp sgt i32 %A, 1
%C = icmp sle i32 %A, 2
define i1 @test23_logical(i32 %A) {
; CHECK-LABEL: @test23_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[A:%.*]], 2
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[D:%.*]] = icmp eq i32 [[A:%.*]], 2
+; CHECK-NEXT: ret i1 [[D]]
;
%B = icmp sgt i32 %A, 1
%C = icmp sle i32 %A, 2
define <2 x i1> @test23vec(<2 x i32> %A) {
; CHECK-LABEL: @test23vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i32> [[A:%.*]], <i32 2, i32 2>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[D:%.*]] = icmp eq <2 x i32> [[A:%.*]], <i32 2, i32 2>
+; CHECK-NEXT: ret <2 x i1> [[D]]
;
%B = icmp sgt <2 x i32> %A, <i32 1, i32 1>
%C = icmp sle <2 x i32> %A, <i32 2, i32 2>
define i1 @test24(i32 %A) {
; CHECK-LABEL: @test24(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[A:%.*]], 2
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[D:%.*]] = icmp sgt i32 [[A:%.*]], 2
+; CHECK-NEXT: ret i1 [[D]]
;
%B = icmp sgt i32 %A, 1
%C = icmp ne i32 %A, 2
define i1 @test24_logical(i32 %A) {
; CHECK-LABEL: @test24_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[A:%.*]], 2
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[D:%.*]] = icmp sgt i32 [[A:%.*]], 2
+; CHECK-NEXT: ret i1 [[D]]
;
%B = icmp sgt i32 %A, 1
%C = icmp ne i32 %A, 2
define i1 @test25(i32 %A) {
; CHECK-LABEL: @test25(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[A:%.*]], -50
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 50
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = icmp ult i32 [[TMP1]], 50
+; CHECK-NEXT: ret i1 [[D]]
;
%B = icmp sge i32 %A, 50
%C = icmp slt i32 %A, 100
define i1 @test25_logical(i32 %A) {
; CHECK-LABEL: @test25_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[A:%.*]], -50
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 50
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = icmp ult i32 [[TMP1]], 50
+; CHECK-NEXT: ret i1 [[D]]
;
%B = icmp sge i32 %A, 50
%C = icmp slt i32 %A, 100
define <2 x i1> @test25vec(<2 x i32> %A) {
; CHECK-LABEL: @test25vec(
; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[A:%.*]], <i32 -50, i32 -50>
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 50, i32 50>
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 50, i32 50>
+; CHECK-NEXT: ret <2 x i1> [[D]]
;
%B = icmp sge <2 x i32> %A, <i32 50, i32 50>
%C = icmp slt <2 x i32> %A, <i32 100, i32 100>
define <2 x i32> @test4(i32 %A, i32 %B){
; CHECK-LABEL: @test4(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A:%.*]], i64 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[B:%.*]], i64 1
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[T43:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[B:%.*]], i64 1
+; CHECK-NEXT: ret <2 x i32> [[T43]]
;
%t38 = zext i32 %A to i64
%t32 = zext i32 %B to i64
define <2 x float> @test5(float %A, float %B) {
; CHECK-LABEL: @test5(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[A:%.*]], i64 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> [[TMP1]], float [[B:%.*]], i64 1
-; CHECK-NEXT: ret <2 x float> [[TMP2]]
+; CHECK-NEXT: [[T43:%.*]] = insertelement <2 x float> [[TMP1]], float [[B:%.*]], i64 1
+; CHECK-NEXT: ret <2 x float> [[T43]]
;
%t37 = bitcast float %A to i32
%t38 = zext i32 %t37 to i64
define <2 x float> @test6(float %A){
; CHECK-LABEL: @test6(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float 4.200000e+01, float poison>, float [[A:%.*]], i64 1
-; CHECK-NEXT: ret <2 x float> [[TMP1]]
+; CHECK-NEXT: [[T35:%.*]] = insertelement <2 x float> <float 4.200000e+01, float poison>, float [[A:%.*]], i64 1
+; CHECK-NEXT: ret <2 x float> [[T35]]
;
%t23 = bitcast float %A to i32
%t24 = zext i32 %t23 to i64
define <2 x i32> @test4(i32 %A, i32 %B){
; CHECK-LABEL: @test4(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A:%.*]], i64 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[B:%.*]], i64 1
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[T43:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[B:%.*]], i64 1
+; CHECK-NEXT: ret <2 x i32> [[T43]]
;
%t38 = zext i32 %A to i64
%t32 = zext i32 %B to i64
define <2 x float> @test5(float %A, float %B) {
; CHECK-LABEL: @test5(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[A:%.*]], i64 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> [[TMP1]], float [[B:%.*]], i64 1
-; CHECK-NEXT: ret <2 x float> [[TMP2]]
+; CHECK-NEXT: [[T43:%.*]] = insertelement <2 x float> [[TMP1]], float [[B:%.*]], i64 1
+; CHECK-NEXT: ret <2 x float> [[T43]]
;
%t37 = bitcast float %A to i32
%t38 = zext i32 %t37 to i64
define <2 x float> @test6(float %A){
; CHECK-LABEL: @test6(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float 4.200000e+01, float poison>, float [[A:%.*]], i64 1
-; CHECK-NEXT: ret <2 x float> [[TMP1]]
+; CHECK-NEXT: [[T35:%.*]] = insertelement <2 x float> <float 4.200000e+01, float poison>, float [[A:%.*]], i64 1
+; CHECK-NEXT: ret <2 x float> [[T35]]
;
%t23 = bitcast float %A to i32
%t24 = zext i32 %t23 to i64
define i32 @test5(i32 %A) {
; CHECK-LABEL: @test5(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -124
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = and i32 [[A:%.*]], -124
+; CHECK-NEXT: ret i32 [[R]]
;
%t1 = or i32 %A, 123
%r = xor i32 %t1, 123
define i8 @test11(i8 %A) {
; CHECK-LABEL: @test11(
; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], -13
-; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[B]], 8
-; CHECK-NEXT: ret i8 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = or i8 [[B]], 8
+; CHECK-NEXT: ret i8 [[C]]
;
%B = or i8 %A, 12
%C = xor i8 %B, 4
define i32 @test40(i32 %x, i32 %y) {
; CHECK-LABEL: @test40(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 [[TMP1]])
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 [[TMP1]])
+; CHECK-NEXT: ret i32 [[RES]]
;
%notx = xor i32 %x, -1
%cmp1 = icmp sgt i32 %notx, %y
define i32 @test41(i32 %x, i32 %y) {
; CHECK-LABEL: @test41(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 [[TMP1]])
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 [[TMP1]])
+; CHECK-NEXT: ret i32 [[RES]]
;
%notx = xor i32 %x, -1
%cmp1 = icmp slt i32 %notx, %y
define i32 @test42(i32 %x, i32 %y) {
; CHECK-LABEL: @test42(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 [[TMP1]])
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 [[TMP1]])
+; CHECK-NEXT: ret i32 [[RES]]
;
%notx = xor i32 %x, -1
%cmp1 = icmp ugt i32 %notx, %y
define i32 @test43(i32 %x, i32 %y) {
; CHECK-LABEL: @test43(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 [[TMP1]])
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 [[TMP1]])
+; CHECK-NEXT: ret i32 [[RES]]
;
%notx = xor i32 %x, -1
%cmp1 = icmp ult i32 %notx, %y
define i32 @test47(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @test47(
; CHECK-NEXT: [[NOTX:%.*]] = xor i32 [[X:%.*]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[NOTX]], i32 [[Y:%.*]])
-; CHECK-NEXT: [[UMIN:%.*]] = xor i32 [[TMP1]], -1
-; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP1]], [[Z:%.*]]
+; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[NOTX]], i32 [[Y:%.*]])
+; CHECK-NEXT: [[UMIN:%.*]] = xor i32 [[UMAX]], -1
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[UMAX]], [[Z:%.*]]
; CHECK-NEXT: [[RES:%.*]] = mul i32 [[ADD]], [[UMIN]]
; CHECK-NEXT: ret i32 [[RES]]
;
define i32 @test48(i32 %x) {
; CHECK-LABEL: @test48(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 -1)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 -1)
+; CHECK-NEXT: ret i32 [[D]]
;
%a = sub i32 -2, %x
%b = icmp sgt i32 %a, 0
define <2 x i32> @test48vec(<2 x i32> %x) {
; CHECK-LABEL: @test48vec(
; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 1, i32 1>
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[TMP1]], <2 x i32> <i32 -1, i32 -1>)
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[TMP1]], <2 x i32> <i32 -1, i32 -1>)
+; CHECK-NEXT: ret <2 x i32> [[D]]
;
%a = sub <2 x i32> <i32 -2, i32 -2>, %x
%b = icmp sgt <2 x i32> %a, zeroinitializer
define i32 @test49(i32 %x) {
; CHECK-LABEL: @test49(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 1, [[X:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP1]], i32 0)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP1]], i32 0)
+; CHECK-NEXT: ret i32 [[D]]
;
%a = add i32 %x, -2
%b = icmp slt i32 %a, -1
define <2 x i32> @test49vec(<2 x i32> %x) {
; CHECK-LABEL: @test49vec(
; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i32> <i32 1, i32 1>, [[X:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[TMP1]], <2 x i32> zeroinitializer)
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[TMP1]], <2 x i32> zeroinitializer)
+; CHECK-NEXT: ret <2 x i32> [[D]]
;
%a = add <2 x i32> %x, <i32 -2, i32 -2>
%b = icmp slt <2 x i32> %a, <i32 -1, i32 -1>
; CHECK-LABEL: @test50(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 1, [[X:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[Y:%.*]], 1
-; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP1]], i32 [[TMP2]])
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[E:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP1]], i32 [[TMP2]])
+; CHECK-NEXT: ret i32 [[E]]
;
%a = add i32 %x, -2
%b = sub i32 -2, %y
; CHECK-LABEL: @test50vec(
; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i32> <i32 1, i32 1>, [[X:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = add <2 x i32> [[Y:%.*]], <i32 1, i32 1>
-; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
-; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+; CHECK-NEXT: [[E:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
+; CHECK-NEXT: ret <2 x i32> [[E]]
;
%a = add <2 x i32> %x, <i32 -2, i32 -2>
%b = sub <2 x i32> <i32 -2, i32 -2>, %y
; CHECK-LABEL: @test51(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 -3, [[X:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[Y:%.*]], -3
-; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 [[TMP2]])
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[E:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 [[TMP2]])
+; CHECK-NEXT: ret i32 [[E]]
;
%a = add i32 %x, 2
%b = sub i32 2, %y
; CHECK-LABEL: @test51vec(
; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i32> <i32 -3, i32 -3>, [[X:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = add <2 x i32> [[Y:%.*]], <i32 -3, i32 -3>
-; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
-; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+; CHECK-NEXT: [[E:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
+; CHECK-NEXT: ret <2 x i32> [[E]]
;
%a = add <2 x i32> %x, <i32 2, i32 2>
%b = sub <2 x i32> <i32 2, i32 2>, %y