* config/pa/tm-hppa.h (PSW_*): Define processor status word masks.
authorJeff Law <law@redhat.com>
Wed, 21 Jun 1995 04:20:15 +0000 (04:20 +0000)
committerJeff Law <law@redhat.com>
Wed, 21 Jun 1995 04:20:15 +0000 (04:20 +0000)
(INSTRUCTION_NULLIFIED): Allow specific targets to override.
* config/pa/tm-hppao.h (INSTRUCTION_NULLIFIED): Define to work
around losing mach kernel behavior.

gdb/ChangeLog
gdb/config/pa/tm-hppao.h

index e72ec9d..d2e073e 100644 (file)
@@ -1,3 +1,10 @@
+Tue Jun 20 22:17:44 1995  Jeff Law  (law@snake.cs.utah.edu)
+
+       * config/pa/tm-hppa.h (PSW_*): Define processor status word masks.
+       (INSTRUCTION_NULLIFIED): Allow specific targets to override.
+       * config/pa/tm-hppao.h (INSTRUCTION_NULLIFIED): Define to work
+       around losing mach kernel behavior.
+
 Tue Jun 20 12:03:36 1995  Stan Shebs  <shebs@andros.cygnus.com>
 
        * monitor.c (monitor_wait): Don't use the watchdog timeout
index aab7274..7df4247 100644 (file)
 /* OSF1 does not need the pc space queue restored.  */
 #define NO_PC_SPACE_QUEUE_RESTORE
 
+/* The mach kernel uses the recovery counter to implement single
+   stepping.  While this greatly simplifies the kernel support
+   necessary for single stepping, it unfortunately does the wrong
+   thing in the presense of a nullified instruction (gives control
+   back two insns after the nullifed insn).  This is an artifact
+   of the HP architecture (recovery counter doesn't tick for
+   nullified insns).
+
+   Do our best to avoid losing in such situations.  */
+#define INSTRUCTION_NULLIFIED \
+(({ \
+    int ipsw = (int)read_register(IPSW_REGNUM); \
+    if (ipsw & PSW_N)  \
+      { \
+        int pcoqt = (int)read_register(PCOQ_TAIL_REGNUM); \
+        write_register(PCOQ_HEAD_REGNUM, pcoqt); \
+        write_register(PCOQ_TAIL_REGNUM, pcoqt + 0x4); \
+        write_register(IPSW_REGNUM, ipsw & ~(PSW_N | PSW_B | PSW_X)); \
+        stop_pc = pcoqt; \
+      } \
+   }), 0) 
+
 /* It's mostly just the common stuff.  */
+
 #include "pa/tm-hppa.h"