add %3,%1,%0\;add %3,%3,%2
add %3,%1,%0\;add %3,%3,%2
add %4,%1,%0\;add %3,%4,%2"
- [(set_attr "type" "fuse_arithlog")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
vaddudm %3,%1,%0\;vaddudm %3,%3,%2
vaddudm %3,%1,%0\;vaddudm %3,%3,%2
vaddudm %4,%1,%0\;vaddudm %3,%4,%2"
- [(set_attr "type" "fuse_vec")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
if ( $kind eq 'vector' ) {
$vchr = "v";
$op = "vaddudm";
- $type = "fuse_vec";
+ $type = "fused_vector";
$mode = "V2DI";
$pred = "altivec_register_operand";
$constraint = "v";
} else {
$vchr = "";
$op = "add";
- $type = "fuse_arithlog";
+ $type = "fused_arith_logical";
$mode = "GPR";
$pred = "gpc_reg_operand";
$constraint = "r";