[X86] Remove SETEQ/SETNE canonicalization code from LowerIntVSETCC_AVX512 to prevent...

The attached test case would previous infinite loop after
r365711.

I'm going to move this to X86ISelDAGToDAG.cpp to get the setcc
to match VPTEST in 32-bit mode in a follow up commit.

llvm-svn: 372543

diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 18a07eb..1cff706 100644 (file)
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -4098,8 +4098,8 @@ bool X86DAGToDAGISel::tryVPTESTM(SDNode *Root, SDValue Setcc,
   if (CC != ISD::SETEQ && CC != ISD::SETNE)
     return false;
 
-  // See if we're comparing against zero. This should have been canonicalized
-  // to RHS during lowering.
+  // See if we're comparing against zero.
+  // FIXME: Handle all zeros on LHS.
   if (!ISD::isBuildVectorAllZeros(Setcc.getOperand(1).getNode()))
     return false;
 

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 7dbd0c1..59670d0 100644 (file)
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -20487,13 +20487,6 @@ static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
 
   ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
 
-  // If this is a seteq make sure any build vectors of all zeros are on the RHS.
-  // This helps with vptestm matching.
-  // TODO: Should we just canonicalize the setcc during DAG combine?
-  if ((SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE) &&
-      ISD::isBuildVectorAllZeros(Op0.getNode()))
-    std::swap(Op0, Op1);
-
   // Prefer SETGT over SETLT.
   if (SetCCOpcode == ISD::SETLT) {
     SetCCOpcode = ISD::getSetCCSwappedOperands(SetCCOpcode);

diff --git a/llvm/test/CodeGen/X86/avx512f-vec-test-testn.ll b/llvm/test/CodeGen/X86/avx512f-vec-test-testn.ll
index 99edd83..58278df 100644 (file)
--- a/llvm/test/CodeGen/X86/avx512f-vec-test-testn.ll
+++ b/llvm/test/CodeGen/X86/avx512f-vec-test-testn.ll
@@ -214,3 +214,30 @@ entry:
   ret i16 %4
 }
 
+define <2 x i64> @setcc_commute(<2 x i64> %a) {
+; X64-LABEL: setcc_commute:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
+; X64-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; X64-NEXT:    vpsubq %xmm0, %xmm1, %xmm1
+; X64-NEXT:    vptestnmq %zmm0, %zmm0, %k1
+; X64-NEXT:    vmovdqa64 %zmm0, %zmm1 {%k1}
+; X64-NEXT:    vmovdqa %xmm1, %xmm0
+; X64-NEXT:    vzeroupper
+; X64-NEXT:    retq
+;
+; X86-LABEL: setcc_commute:
+; X86:       # %bb.0:
+; X86-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
+; X86-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; X86-NEXT:    vpsubq %xmm0, %xmm2, %xmm1
+; X86-NEXT:    vpcmpeqq %zmm0, %zmm2, %k1
+; X86-NEXT:    vmovdqa64 %zmm0, %zmm1 {%k1}
+; X86-NEXT:    vmovdqa %xmm1, %xmm0
+; X86-NEXT:    vzeroupper
+; X86-NEXT:    retl
+  %1 = sub <2 x i64> zeroinitializer, %a
+  %2 = icmp eq <2 x i64> %a, zeroinitializer
+  %3 = select <2 x i1> %2, <2 x i64> %a, <2 x i64> %1
+  ret <2 x i64> %3
+}