powerpc/mpc85xx: Workaround for erratum CPU_A011

Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.

Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 35c2b1a..4e1a54a 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -52,6 +52,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        if (SVR_MAJ(svr) < 3)
                puts("Work-around for Erratum CPU22 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
+       /*
+        * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+        * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+        */
+       if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3)
+               puts("Work-around for Erratum CPU-A011 enabled\n");
+#endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
        puts("Work-around for Erratum CPU-A003999 enabled\n");
 #endif

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index d7e80fc..fc6c287 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -308,8 +308,14 @@ int cpu_init_r(void)
        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 #endif
 
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
-       if (SVR_MAJ(svr) < 3) {
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
+       defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
+       /*
+        * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+        * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+        * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+        */
+       if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) {
                flush_dcache();
                mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
                sync();

diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index fe3b6d6..36c79d3 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -143,17 +143,29 @@ __secondary_start_page:
        mtspr   L1CSR2,r8
 #endif
 
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
-       /* apply to P4080 rev 1 and rev 2 */
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
+       defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
+       /*
+        * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+        * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+        * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+        */
        mfspr   r3,SPRN_SVR
+       rlwinm  r6,r3,24,~0x800         /* clear E bit */
+
+       lis     r5,SVR_P4080@h
+       ori     r5,r5,SVR_P4080@l
+       cmpw    r6,r5
+       bne     1f
+
        rlwinm  r3,r3,0,0xf0
-       li      r4,0x30
-       cmpw    r3,r4
+       li      r5,0x30
+       cmpw    r3,r5
        bge     2f
-
-       mfspr   r8,L1CSR2
-       oris    r8,r8,(L1CSR2_DCWS)@h
-       mtspr   L1CSR2,r8
+1:
+       mfspr   r3,L1CSR2
+       oris    r3,r3,(L1CSR2_DCWS)@h
+       mtspr   L1CSR2,r3
 2:
 #endif
 

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index f93ab62..b6c44bb 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -349,6 +349,7 @@
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
@@ -373,6 +374,7 @@
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
@@ -460,6 +462,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136
 #define CONFIG_SYS_P4080_ERRATUM_CPU22
+#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001