soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init()
authorYang Yingliang <yangyingliang@huawei.com>
Tue, 18 Oct 2022 02:31:49 +0000 (10:31 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 31 Dec 2022 12:31:50 +0000 (13:31 +0100)
[ Upstream commit 8fbf94fea0b4e187ca9100936c5429f96b8a4e44 ]

The device_node pointer returned by of_find_matching_node() with
refcount incremented, when finish using it, the refcount need be
decreased.

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/soc/sifive/sifive_ccache.c

index 98269d0..3684f5b 100644 (file)
@@ -215,12 +215,16 @@ static int __init sifive_ccache_init(void)
        if (!np)
                return -ENODEV;
 
-       if (of_address_to_resource(np, 0, &res))
-               return -ENODEV;
+       if (of_address_to_resource(np, 0, &res)) {
+               rc = -ENODEV;
+               goto err_node_put;
+       }
 
        ccache_base = ioremap(res.start, resource_size(&res));
-       if (!ccache_base)
-               return -ENOMEM;
+       if (!ccache_base) {
+               rc = -ENOMEM;
+               goto err_node_put;
+       }
 
        if (of_property_read_u32(np, "cache-level", &level)) {
                rc = -ENOENT;
@@ -243,6 +247,7 @@ static int __init sifive_ccache_init(void)
                        goto err_free_irq;
                }
        }
+       of_node_put(np);
 
        ccache_config_read();
 
@@ -259,6 +264,8 @@ err_free_irq:
                free_irq(g_irq[i], NULL);
 err_unmap:
        iounmap(ccache_base);
+err_node_put:
+       of_node_put(np);
        return rc;
 }