Merge remote-tracking branch 'airlied/drm-core-next' into drm-intel-next-queued

Backmerge of drm-next to resolve a few ugly conflicts and to get a few
fixes from 3.4-rc6 (which drm-next has already merged). Note that this
merge also restricts the stencil cache lra evict policy workaround to
snb (as it should) - I had to frob the code anyway because the
CM0_MASK_SHIFT define died in the masked bit cleanups.

We need the backmerge to get Paulo Zanoni's infoframe regression fix
for gm45 - further bugfixes from him touch the same area and would
needlessly conflict.

Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --cc drivers/gpu/drm/i915/i915_gem.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a46ed26,c77bfa9..206b9bb
--- 1/drivers/gpu/drm/i915/i915_gem_execbuffer.c
--- 2/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@@ -1116,11 -1116,11 +1116,17 @@@ i915_gem_do_execbuffer(struct drm_devic
                        return -EINVAL;
                }
  
 +              if (INTEL_INFO(dev)->gen >= 5) {
 +                      DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
 +                      return -EINVAL;
 +              }
 +
+               if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
+                       DRM_DEBUG("execbuf with %u cliprects\n",
+                                 args->num_cliprects);
+                       return -EINVAL;
+               }
++
                cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
                                    GFP_KERNEL);
                if (cliprects == NULL) {

diff --cc drivers/gpu/drm/i915/intel_display.c
index e20f804,8c239f2..6b41390
--- 1/drivers/gpu/drm/i915/intel_display.c
--- 2/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@@ -5849,15 -5793,21 +5854,21 @@@ static int intel_gen6_queue_flip(struc
        if (ret)
                goto err_unpin;
  
 -      OUT_RING(MI_DISPLAY_FLIP |
 -               MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
 -      OUT_RING(fb->pitches[0] | obj->tiling_mode);
 -      OUT_RING(obj->gtt_offset);
 +      intel_ring_emit(ring, MI_DISPLAY_FLIP |
 +                      MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
 +      intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
 +      intel_ring_emit(ring, obj->gtt_offset);
  
-       pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
+       /* Contrary to the suggestions in the documentation,
+        * "Enable Panel Fitter" does not seem to be required when page
+        * flipping with a non-native mode, and worse causes a normal
+        * modeset to fail.
+        * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
+        */
+       pf = 0;
        pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
 -      OUT_RING(pf | pipesrc);
 -      ADVANCE_LP_RING();
 +      intel_ring_emit(ring, pf | pipesrc);
 +      intel_ring_advance(ring);
        return 0;
  
  err_unpin:

diff --cc drivers/gpu/drm/i915/intel_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_hdmi.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_ringbuffer.c
index 3aabe8d,b5ef7c1..b59b6d5
--- 1/drivers/gpu/drm/i915/intel_ringbuffer.c
--- 2/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@@ -414,9 -415,19 +414,19 @@@ static int init_render_ring(struct inte
                        return ret;
        }
  
 -      if (INTEL_INFO(dev)->gen >= 6) {
 -              I915_WRITE(INSTPM,
 -                         INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
 -
++      if (IS_GEN6(dev)) {
+               /* From the Sandybridge PRM, volume 1 part 3, page 24:
+                * "If this bit is set, STCunit will have LRA as replacement
+                *  policy. [...] This bit must be reset.  LRA replacement
+                *  policy is not supported."
+                */
+               I915_WRITE(CACHE_MODE_0,
 -                         CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
++                         _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
+       }
+ 
 +      if (INTEL_INFO(dev)->gen >= 6)
 +              I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 +
        return ret;
  }
  

diff --cc drivers/gpu/drm/i915/intel_sdvo.c
index 9b3a5f9,3d9dfa5..7d3f238
--- 1/drivers/gpu/drm/i915/intel_sdvo.c
--- 2/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@@ -745,21 -745,26 +745,26 @@@ static void intel_sdvo_get_dtd_from_mod
        uint16_t width, height;
        uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
        uint16_t h_sync_offset, v_sync_offset;
+       int mode_clock;
  
 -      width = mode->crtc_hdisplay;
 -      height = mode->crtc_vdisplay;
 +      width = mode->hdisplay;
 +      height = mode->vdisplay;
  
        /* do some mode translations */
 -      h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
 -      h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 +      h_blank_len = mode->htotal - mode->hdisplay;
 +      h_sync_len = mode->hsync_end - mode->hsync_start;
  
 -      v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
 -      v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 +      v_blank_len = mode->vtotal - mode->vdisplay;
 +      v_sync_len = mode->vsync_end - mode->vsync_start;
  
 -      h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
 -      v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
 +      h_sync_offset = mode->hsync_start - mode->hdisplay;
 +      v_sync_offset = mode->vsync_start - mode->vdisplay;
  
-       dtd->part1.clock = mode->clock / 10;
+       mode_clock = mode->clock;
+       mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
+       mode_clock /= 10;
+       dtd->part1.clock = mode_clock;
+ 
        dtd->part1.h_active = width & 0xff;
        dtd->part1.h_blank = h_blank_len & 0xff;
        dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |