drm/amdgpu: enable async gfx ring for navi14

Same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 74066e1..f9bef31 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -389,7 +389,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
                                dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
        }
 
-       if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring) {
+       if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
                /* create MQD for each KGQ */
                for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
                        ring = &adev->gfx.gfx_ring[i];
@@ -437,7 +437,7 @@ void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
        struct amdgpu_ring *ring = NULL;
        int i;
 
-       if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring) {
+       if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
                for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
                        ring = &adev->gfx.gfx_ring[i];
                        kfree(adev->gfx.me.mqd_backup[i]);
@@ -456,7 +456,7 @@ void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
        }
 
        ring = &adev->gfx.kiq.ring;
-       if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring)
+       if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring)
                kfree(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]);
        kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
        amdgpu_bo_free_kernel(&ring->mqd_obj,