clk: qcom: gpucc-sm8150: Update the gpu_cc_pll1 config

[ Upstream commit 6ebd9a4f8b8d2b35cf965a04849c4ba763722f13 ]

Update the test_ctl_hi_val and test_ctl_hi1_val of gpu_cc_pll1
as per latest HW recommendation.

Fixes: 0cef71f2ccc8 ("clk: qcom: Add graphics clock controller driver for SM8150")
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231122042814.4158076-1-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/qcom/gpucc-sm8150.c b/drivers/clk/qcom/gpucc-sm8150.c
index 8422fd0..c89a5b5 100644 (file)
--- a/drivers/clk/qcom/gpucc-sm8150.c
+++ b/drivers/clk/qcom/gpucc-sm8150.c
@@ -37,8 +37,8 @@ static struct alpha_pll_config gpu_cc_pll1_config = {
        .config_ctl_hi_val = 0x00002267,
        .config_ctl_hi1_val = 0x00000024,
        .test_ctl_val = 0x00000000,
-       .test_ctl_hi_val = 0x00000002,
-       .test_ctl_hi1_val = 0x00000000,
+       .test_ctl_hi_val = 0x00000000,
+       .test_ctl_hi1_val = 0x00000020,
        .user_ctl_val = 0x00000000,
        .user_ctl_hi_val = 0x00000805,
        .user_ctl_hi1_val = 0x000000d0,