drm/amdgpu: add pcie port indirect read and write on nv

This patch is to add pcie port indirect read/write callback for nv
series. They will be used for new asic.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index edaac24..483834a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -53,6 +53,8 @@ struct amdgpu_nbio_funcs {
        u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
        u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
        u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
+       u32 (*get_pcie_port_index_offset)(struct amdgpu_device *adev);
+       u32 (*get_pcie_port_data_offset)(struct amdgpu_device *adev);
        u32 (*get_rev_id)(struct amdgpu_device *adev);
        void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
        void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 1666d43..46d6fd0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -95,6 +95,21 @@ static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
        return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 }
 
+static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
+{
+       unsigned long flags, address, data;
+       u32 r;
+       address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
+       data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
+
+       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       WREG32(address, reg * 4);
+       (void)RREG32(address);
+       r = RREG32(data);
+       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       return r;
+}
+
 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 {
        unsigned long address, data;
@@ -105,6 +120,21 @@ static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
        amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 }
 
+static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+{
+       unsigned long flags, address, data;
+
+       address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
+       data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
+
+       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       WREG32(address, reg * 4);
+       (void)RREG32(address);
+       WREG32(data, v);
+       (void)RREG32(data);
+       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+}
+
 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 {
        unsigned long flags, address, data;
@@ -711,6 +741,8 @@ static int nv_common_early_init(void *handle)
        adev->pcie_wreg = &nv_pcie_wreg;
        adev->pcie_rreg64 = &nv_pcie_rreg64;
        adev->pcie_wreg64 = &nv_pcie_wreg64;
+       adev->pciep_rreg = &nv_pcie_port_rreg;
+       adev->pciep_wreg = &nv_pcie_port_wreg;
 
        /* TODO: will add them during VCN v2 implementation */
        adev->uvd_ctx_rreg = NULL;