dt-bindings: add mmio-based syscon mux controller DT bindings
authorPhilipp Zabel <p.zabel@pengutronix.de>
Sun, 14 May 2017 19:51:15 +0000 (21:51 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 3 Jun 2017 10:29:26 +0000 (19:29 +0900)
This adds device tree binding documentation for mmio-based syscon
multiplexers controlled by a bitfields in a syscon register range.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Documentation/devicetree/bindings/mux/mmio-mux.txt [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/mux/mmio-mux.txt b/Documentation/devicetree/bindings/mux/mmio-mux.txt
new file mode 100644 (file)
index 0000000..a9bfb4d
--- /dev/null
@@ -0,0 +1,60 @@
+MMIO register bitfield-based multiplexer controller bindings
+
+Define register bitfields to be used to control multiplexers. The parent
+device tree node must be a syscon node to provide register access.
+
+Required properties:
+- compatible : "mmio-mux"
+- #mux-control-cells : <1>
+- mux-reg-masks : an array of register offset and pre-shifted bitfield mask
+                  pairs, each describing a single mux control.
+* Standard mux-controller bindings as decribed in mux-controller.txt
+
+Optional properties:
+- idle-states : if present, the state the muxes will have when idle. The
+               special state MUX_IDLE_AS_IS is the default.
+
+The multiplexer state of each multiplexer is defined as the value of the
+bitfield described by the corresponding register offset and bitfield mask pair
+in the mux-reg-masks array, accessed through the parent syscon.
+
+Example:
+
+       syscon {
+               compatible = "syscon";
+
+               mux: mux-controller {
+                       compatible = "mmio-mux";
+                       #mux-control-cells = <1>;
+
+                       mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
+                                       <0x3 0x40>, /* 1: reg 0x3, bit 6 */
+                       idle-states = <MUX_IDLE_AS_IS>, <0>;
+               };
+       };
+
+       video-mux {
+               compatible = "video-mux";
+               mux-controls = <&mux 0>;
+
+               ports {
+                       /* inputs 0..3 */
+                       port@0 {
+                               reg = <0>;
+                       };
+                       port@1 {
+                               reg = <1>;
+                       };
+                       port@2 {
+                               reg = <2>;
+                       };
+                       port@3 {
+                               reg = <3>;
+                       };
+
+                       /* output */
+                       port@4 {
+                               reg = <4>;
+                       };
+               };
+       };