free_pages((unsigned long)address, order);
}
-int drm_ati_pcigart_cleanup(struct drm_device *dev, struct ati_pcigart_info *gart_info)
+int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
{
struct drm_sg_mem *entry = dev->sg;
unsigned long pages;
}
EXPORT_SYMBOL(drm_ati_pcigart_cleanup);
-int drm_ati_pcigart_init(struct drm_device *dev, struct ati_pcigart_info *gart_info)
+int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
{
struct drm_sg_mem *entry = dev->sg;
void *address = NULL;
#include "drm_hashtab.h"
#include "drm_internal.h"
+struct drm_device;
struct drm_file;
/* If you want the memory alloc debug functionality, change define below */
#define DRM_OBJECT_HASH_ORDER 12
#define DRM_FILE_PAGE_OFFSET_START ((0xFFFFFFFFUL >> PAGE_SHIFT) + 1)
#define DRM_FILE_PAGE_OFFSET_SIZE ((0xFFFFFFFFUL >> PAGE_SHIFT) * 16)
+/*
+ * This should be small enough to allow the use of kmalloc for hash tables
+ * instead of vmalloc.
+ */
+
+#define DRM_FILE_HASH_ORDER 8
#define DRM_MM_INIT_MAX_PAGES 256
/*@}*/
#if DRM_DEBUG_CODE
#define DRM_DEBUG(fmt, arg...) \
do { \
- if ( drm_debug ) \
+ if ( drm_debug ) \
printk(KERN_DEBUG \
"[" DRM_NAME ":%s] " fmt , \
__FUNCTION__ , ##arg); \
return -EFAULT; \
}
-struct drm_device;
-struct drm_file;
-
/**
* Ioctl function type.
*
struct drm_freelist freelist;
};
-/*
- * This should be small enough to allow the use of kmalloc for hash tables
- * instead of vmalloc.
- */
-#define DRM_FILE_HASH_ORDER 8
enum drm_ref_type {
- _DRM_REF_USE=0,
+ _DRM_REF_USE = 0,
_DRM_REF_TYPE1,
_DRM_NO_REF_TYPES
};
/**
* AGP data.
*
- * \sa drm_agp_init)() and drm_device::agp.
+ * \sa drm_agp_init() and drm_device::agp.
*/
struct drm_agp_head {
DRM_AGP_KERN agp_info; /**< AGP device information */
struct list_head memory;
unsigned long mode; /**< AGP mode */
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,11)
- struct agp_bridge_data *bridge;
+ struct agp_bridge_data *bridge;
#endif
int enabled; /**< whether the AGP bus as been enabled */
int acquired; /**< whether the AGP device has been acquired */
#define DRM_ATI_GART_PCIE 2
#define DRM_ATI_GART_IGP 3
-struct ati_pcigart_info {
+struct drm_ati_pcigart_info {
int gart_table_location;
int gart_reg_if;
void *addr;
int (*dma_ioctl) (struct drm_device *dev, void *data, struct drm_file *file_priv);
void (*dma_ready) (struct drm_device *);
int (*dma_quiescent) (struct drm_device *);
- int (*context_ctor) (struct drm_device * dev, int context);
- int (*context_dtor) (struct drm_device * dev, int context);
- int (*kernel_context_switch) (struct drm_device * dev, int old,
+ int (*context_ctor) (struct drm_device *dev, int context);
+ int (*context_dtor) (struct drm_device *dev, int context);
+ int (*kernel_context_switch) (struct drm_device *dev, int old,
int new);
- void (*kernel_context_switch_unlock) (struct drm_device * dev);
- int (*vblank_wait) (struct drm_device * dev, unsigned int *sequence);
- int (*vblank_wait2) (struct drm_device * dev, unsigned int *sequence);
- int (*dri_library_name) (struct drm_device * dev, char * buf);
+ void (*kernel_context_switch_unlock) (struct drm_device *dev);
+ int (*vblank_wait) (struct drm_device *dev, unsigned int *sequence);
+ int (*vblank_wait2) (struct drm_device *dev, unsigned int *sequence);
+ int (*dri_library_name) (struct drm_device *dev, char * buf);
/**
* Called by \c drm_device_is_agp. Typically used to determine if a
* card is absolutely \b not AGP (return of 0), absolutely \b is AGP
* (return of 1), or may or may not be AGP (return of 2).
*/
- int (*device_is_agp) (struct drm_device * dev);
+ int (*device_is_agp) (struct drm_device *dev);
/* these have to be filled in */
irqreturn_t(*irq_handler) (DRM_IRQ_ARGS);
- void (*irq_preinstall) (struct drm_device * dev);
- void (*irq_postinstall) (struct drm_device * dev);
- void (*irq_uninstall) (struct drm_device * dev);
+ void (*irq_preinstall) (struct drm_device *dev);
+ void (*irq_postinstall) (struct drm_device *dev);
+ void (*irq_uninstall) (struct drm_device *dev);
void (*reclaim_buffers) (struct drm_device *dev,
struct drm_file *file_priv);
void (*reclaim_buffers_locked) (struct drm_device *dev,
struct drm_file *file_priv);
void (*reclaim_buffers_idlelocked) (struct drm_device *dev,
struct drm_file *file_priv);
- unsigned long (*get_map_ofs) (struct drm_map * map);
- unsigned long (*get_reg_ofs) (struct drm_device * dev);
- void (*set_version) (struct drm_device * dev, struct drm_set_version * sv);
+ unsigned long (*get_map_ofs) (struct drm_map *map);
+ unsigned long (*get_reg_ofs) (struct drm_device *dev);
+ void (*set_version) (struct drm_device *dev,
+ struct drm_set_version *sv);
struct drm_fence_driver *fence_driver;
struct drm_bo_driver *bo_driver;
struct drm_file *file_priv);
/* ATI PCIGART support (ati_pcigart.h) */
-extern int drm_ati_pcigart_init(struct drm_device *dev, struct ati_pcigart_info *gart_info);
-extern int drm_ati_pcigart_cleanup(struct drm_device *dev, struct ati_pcigart_info *gart_info);
+extern int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
+extern int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
extern drm_dma_handle_t *drm_pci_alloc(struct drm_device *dev, size_t size,
size_t align, dma_addr_t maxaddr);
struct drm_sysfs_class;
extern struct class *drm_sysfs_create(struct module *owner, char *name);
extern void drm_sysfs_destroy(void);
-extern int drm_sysfs_device_add(struct drm_device *dev, struct drm_head * head);
+extern int drm_sysfs_device_add(struct drm_device *dev, struct drm_head *head);
extern void drm_sysfs_device_remove(struct drm_device *dev);
/*
static __inline__ int drm_device_is_agp(struct drm_device *dev)
{
if ( dev->driver->device_is_agp != NULL ) {
- int err = (*dev->driver->device_is_agp)( dev );
+ int err = (*dev->driver->device_is_agp)(dev);
if (err != 2) {
return err;
* Verifies the AGP device has been initialized and acquired and fills in the
* drm_agp_info structure with the information in drm_agp_head::agp_info.
*/
-int drm_agp_info(struct drm_device * dev, struct drm_agp_info *info)
+int drm_agp_info(struct drm_device *dev, struct drm_agp_info *info)
{
DRM_AGP_KERN *kern;
int drm_agp_acquire_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
- return drm_agp_acquire( (struct drm_device *) file_priv->head->dev );
+ return drm_agp_acquire((struct drm_device *) file_priv->head->dev);
}
/**
if (!(head->bridge = agp_backend_acquire(dev->pdev))) {
drm_free(head, sizeof(*head), DRM_MEM_AGPLISTS);
return NULL;
- }
+ }
agp_copy_info(head->bridge, &head->agp_info);
agp_backend_release(head->bridge);
} else {
return -ENOMEM;
memset(entry, 0, sizeof(*entry));
entry->priv = priv;
- entry->hash_item.key = (unsigned long) magic;
+ entry->hash_item.key = (unsigned long)magic;
mutex_lock(&dev->struct_mutex);
drm_ht_insert_item(&dev->magiclist, &entry->hash_item);
list_add_tail(&entry->head, &dev->magicfree);
DRM_DEBUG("%d\n", magic);
mutex_lock(&dev->struct_mutex);
- if (drm_ht_find_item(&dev->magiclist, (unsigned long) magic, &hash)) {
+ if (drm_ht_find_item(&dev->magiclist, (unsigned long)magic, &hash)) {
mutex_unlock(&dev->struct_mutex);
return -EINVAL;
}
if (drm_core_has_MTRR(dev)) {
if (map->type == _DRM_FRAME_BUFFER ||
(map->flags & _DRM_WRITE_COMBINING)) {
- map->mtrr = mtrr_add(map->offset, map->size,
- MTRR_TYPE_WRCOMB, 1);
+ map->mtrr = mtrr_add(map->offset, map->size,
+ MTRR_TYPE_WRCOMB, 1);
}
}
- if (map->type == _DRM_REGISTERS)
+ if (map->type == _DRM_REGISTERS) {
map->handle = ioremap(map->offset, map->size);
+ if (!map->handle) {
+ drm_free(map, sizeof(*map), DRM_MEM_MAPS);
+ return -ENOMEM;
+ }
+ }
break;
case _DRM_SHM:
list = drm_find_matching_map(dev, map);
}
}
- if (!found) {
+ if (!found)
return -EINVAL;
- }
+
/* List has wrapped around to the head pointer, or it's empty and we
* didn't find anything.
*/
*
* Frees any pages and buffers associated with the given entry.
*/
-static void drm_cleanup_buf_error(struct drm_device *dev, struct drm_buf_entry * entry)
+static void drm_cleanup_buf_error(struct drm_device *dev,
+ struct drm_buf_entry *entry)
{
int i;
#if __OS_HAS_AGP
/**
- * Add AGP buffers for DMA transfers
+ * Add AGP buffers for DMA transfers.
*
* \param dev struct drm_device to which the buffers are to be added.
* \param request pointer to a struct drm_buf_desc describing the request.
* reallocates the buffer list of the same size order to accommodate the new
* buffers.
*/
-int drm_addbufs_agp(struct drm_device *dev, struct drm_buf_desc * request)
+int drm_addbufs_agp(struct drm_device *dev, struct drm_buf_desc *request)
{
struct drm_device_dma *dma = dev->dma;
struct drm_buf_entry *entry;
EXPORT_SYMBOL(drm_addbufs_agp);
#endif /* __OS_HAS_AGP */
-int drm_addbufs_pci(struct drm_device *dev, struct drm_buf_desc * request)
+int drm_addbufs_pci(struct drm_device *dev, struct drm_buf_desc *request)
{
struct drm_device_dma *dma = dev->dma;
int count;
}
EXPORT_SYMBOL(drm_addbufs_pci);
-static int drm_addbufs_sg(struct drm_device *dev, struct drm_buf_desc * request)
+static int drm_addbufs_sg(struct drm_device *dev, struct drm_buf_desc *request)
{
struct drm_device_dma *dma = dev->dma;
struct drm_buf_entry *entry;
*
* Allocate and initialize a drm_device_dma structure.
*/
-int drm_dma_setup(struct drm_device * dev)
+int drm_dma_setup(struct drm_device *dev)
{
int i;
* Free all pages associated with DMA buffers, the buffers and pages lists, and
* finally the drm_device::dma structure itself.
*/
-void drm_dma_takedown(struct drm_device * dev)
+void drm_dma_takedown(struct drm_device *dev)
{
struct drm_device_dma *dma = dev->dma;
int i, j;
*
* Resets the fields of \p buf.
*/
-void drm_free_buffer(struct drm_device * dev, struct drm_buf * buf)
+void drm_free_buffer(struct drm_device *dev, struct drm_buf *buf)
{
if (!buf)
return;
if (dev->unique) {
drm_free(dev->unique, strlen(dev->unique) + 1, DRM_MEM_DRIVER);
- dev->unique=NULL;
- dev->unique_len=0;
+ dev->unique = NULL;
+ dev->unique_len = 0;
}
if (dev->irq_enabled)
spin_unlock(&dev->count_lock);
}
- out:
+out:
mutex_lock(&dev->struct_mutex);
BUG_ON((dev->dev_mapping != NULL) &&
(dev->dev_mapping != inode->i_mapping));
int minor = iminor(inode);
struct drm_file *priv;
int ret;
- int i,j;
+ int i, j;
if (filp->f_flags & O_EXCL)
return -EBUSY; /* No exclusive opens */
INIT_LIST_HEAD(&priv->lhead);
INIT_LIST_HEAD(&priv->refd_objects);
- for (i=0; i<_DRM_NO_REF_TYPES; ++i) {
- ret = drm_ht_create(&priv->refd_object_hash[i], DRM_FILE_HASH_ORDER);
+ for (i = 0; i < _DRM_NO_REF_TYPES; ++i) {
+ ret = drm_ht_create(&priv->refd_object_hash[i],
+ DRM_FILE_HASH_ORDER);
if (ret)
break;
}
if (ret) {
- for(j = 0; j < i; ++j)
+ for (j = 0; j < i; ++j)
drm_ht_remove(&priv->refd_object_hash[j]);
goto out_free;
}
/*
* Free leftover ref objects created by me. Note that we cannot use
- * list_for_each() here, as the struct_mutex may be temporarily released
- * by the remove_() functions, and thus the lists may be altered.
+ * list_for_each() here, as the struct_mutex may be temporarily
+ * released by the remove_() functions, and thus the lists may be
+ * altered.
* Also, a drm_remove_ref_object() will not remove it
* from the list unless its refcount is 1.
*/
head = &priv->refd_objects;
}
- for(i = 0; i < _DRM_NO_REF_TYPES; ++i) {
+ for (i = 0; i < _DRM_NO_REF_TYPES; ++i)
drm_ht_remove(&priv->refd_object_hash[i]);
- }
}
/**
#include "drm_hashtab.h"
#include <linux/hash.h>
-int drm_ht_create(struct drm_open_hash * ht, unsigned int order)
+int drm_ht_create(struct drm_open_hash *ht, unsigned int order)
{
unsigned int i;
return 0;
}
-void drm_ht_verbose_list(struct drm_open_hash * ht, unsigned long key)
+void drm_ht_verbose_list(struct drm_open_hash *ht, unsigned long key)
{
struct drm_hash_item *entry;
struct hlist_head *h_list;
}
}
-static struct hlist_node *drm_ht_find_key(struct drm_open_hash * ht,
+static struct hlist_node *drm_ht_find_key(struct drm_open_hash *ht,
unsigned long key)
{
struct drm_hash_item *entry;
return NULL;
}
-int drm_ht_insert_item(struct drm_open_hash * ht, struct drm_hash_item * item)
+int drm_ht_insert_item(struct drm_open_hash *ht, struct drm_hash_item *item)
{
struct drm_hash_item *entry;
struct hlist_head *h_list;
* Just insert an item and return any "bits" bit key that hasn't been
* used before.
*/
-int drm_ht_just_insert_please(struct drm_open_hash * ht, struct drm_hash_item * item,
+int drm_ht_just_insert_please(struct drm_open_hash *ht,
+ struct drm_hash_item *item,
unsigned long seed, int bits, int shift,
unsigned long add)
{
return 0;
}
-int drm_ht_find_item(struct drm_open_hash * ht, unsigned long key,
- struct drm_hash_item ** item)
+int drm_ht_find_item(struct drm_open_hash *ht, unsigned long key,
+ struct drm_hash_item **item)
{
struct hlist_node *list;
return 0;
}
-int drm_ht_remove_key(struct drm_open_hash * ht, unsigned long key)
+int drm_ht_remove_key(struct drm_open_hash *ht, unsigned long key)
{
struct hlist_node *list;
return -EINVAL;
}
-int drm_ht_remove_item(struct drm_open_hash * ht, struct drm_hash_item * item)
+int drm_ht_remove_item(struct drm_open_hash *ht, struct drm_hash_item *item)
{
hlist_del_init(&item->head);
ht->fill--;
return 0;
}
-void drm_ht_remove(struct drm_open_hash * ht)
+void drm_ht_remove(struct drm_open_hash *ht)
{
if (ht->table) {
if (ht->use_vmalloc)
*/
static void drm_locked_tasklet_func(unsigned long data)
{
- struct drm_device *dev = (struct drm_device*)data;
+ struct drm_device *dev = (struct drm_device *)data;
unsigned long irqflags;
spin_lock_irqsave(&dev->tasklet_lock, irqflags);
* context, it must not make any assumptions about this. Also, the HW lock will
* be held with the kernel context or any client context.
*/
-void drm_locked_tasklet(struct drm_device *dev, void (*func)(struct drm_device*))
+void drm_locked_tasklet(struct drm_device *dev, void (*func)(struct drm_device *))
{
unsigned long irqflags;
static DECLARE_TASKLET(drm_tasklet, drm_locked_tasklet_func, 0);
.lock = SPIN_LOCK_UNLOCKED
};
-static inline size_t drm_size_align(size_t size) {
-
+static inline size_t drm_size_align(size_t size)
+{
size_t tmpSize = 4;
if (size > PAGE_SIZE)
return PAGE_ALIGN(size);
- while(tmpSize < size)
+ while (tmpSize < size)
tmpSize <<= 1;
return (size_t) tmpSize;
* drm_memory.h.
*/
-/* Need the 4-argument version of vmap(). */
#if __OS_HAS_AGP
#include <linux/vmalloc.h>
*
* This function is for internal use in the Linux-specific DRM core code.
*/
-void __drm_pci_free(struct drm_device * dev, drm_dma_handle_t *dmah)
+void __drm_pci_free(struct drm_device *dev, drm_dma_handle_t *dmah)
{
unsigned long addr;
size_t sz;
/**
* \brief Free a PCI consistent memory block
*/
-void drm_pci_free(struct drm_device * dev, drm_dma_handle_t *dmah)
+void drm_pci_free(struct drm_device *dev, drm_dma_handle_t *dmah)
{
__drm_pci_free(dev, dmah);
kfree(dmah);
else
type = types[map->type];
DRM_PROC_PRINT("%4d 0x%08lx 0x%08lx %4.4s 0x%02x 0x%08lx ",
- i,
- map->offset,
- map->size, type, map->flags,
- (unsigned long) r_list->user_token);
+ i,
+ map->offset,
+ map->size, type, map->flags,
+ (unsigned long) r_list->user_token);
if (map->mtrr < 0) {
DRM_PROC_PRINT("none\n");
if (drm_ht_find_item(&sman->user_hash_tab, key, &hash_item))
return -EINVAL;
- memblock_item = drm_hash_entry(hash_item, struct drm_memblock_item, user_hash);
+ memblock_item = drm_hash_entry(hash_item, struct drm_memblock_item,
+ user_hash);
drm_sman_free(memblock_item);
return 0;
}
struct proc_dir_entry *drm_proc_root;
static int drm_fill_in_dev(struct drm_device * dev, struct pci_dev *pdev,
- const struct pci_device_id *ent,
- struct drm_driver *driver)
+ const struct pci_device_id *ent,
+ struct drm_driver *driver)
{
int retcode;
* Try and register, if we fail to register, backout previous work.
*/
int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
- struct drm_driver *driver)
+ struct drm_driver *driver)
{
struct drm_device *dev;
int ret;
drm_proc_cleanup(minor, drm_proc_root, head->dev_root);
drm_sysfs_device_remove(head->dev);
- *head = (struct drm_head){.dev = NULL};
+ *head = (struct drm_head) {.dev = NULL};
drm_heads[minor] = NULL;
return 0;
}
EXPORT_SYMBOL(drm_ttm_get_page);
-
-
-
int drm_ttm_set_user(struct drm_ttm *ttm,
struct task_struct *tsk,
int write,
return 0;
}
-
-
int drm_ttm_populate(struct drm_ttm *ttm)
{
struct page *page;
dmah.size = map->size;
__drm_pci_free(dev, &dmah);
break;
- case _DRM_TTM:
+ case _DRM_TTM:
BUG_ON(1);
break;
}
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
#endif
if (io_remap_pfn_range(vma, vma->vm_start,
- (map->offset + offset) >> PAGE_SHIFT,
- vma->vm_end - vma->vm_start,
- vma->vm_page_prot))
+ (map->offset + offset) >> PAGE_SHIFT,
+ vma->vm_end - vma->vm_start,
+ vma->vm_page_prot))
return -EAGAIN;
DRM_DEBUG(" Type = %d; start = 0x%lx, end = 0x%lx,"
" offset = 0x%lx\n",
}
struct drm_ioctl_desc i810_ioctls[] = {
- DRM_IOCTL_DEF(DRM_I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+ DRM_IOCTL_DEF(DRM_I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_I810_VERTEX, i810_dma_vertex, DRM_AUTH),
DRM_IOCTL_DEF(DRM_I810_CLEAR, i810_clear_bufs, DRM_AUTH),
DRM_IOCTL_DEF(DRM_I810_FLUSH, i810_flush_ioctl, DRM_AUTH),
} drm_i915_batchbuffer32_t;
static int compat_i915_batchbuffer(struct file *file, unsigned int cmd,
- unsigned long arg)
+ unsigned long arg)
{
drm_i915_batchbuffer32_t batchbuffer32;
drm_i915_batchbuffer_t __user *batchbuffer;
} drm_i915_cmdbuffer32_t;
static int compat_i915_cmdbuffer(struct file *file, unsigned int cmd,
- unsigned long arg)
+ unsigned long arg)
{
drm_i915_cmdbuffer32_t cmdbuffer32;
drm_i915_cmdbuffer_t __user *cmdbuffer;
} drm_i915_irq_emit32_t;
static int compat_i915_irq_emit(struct file *file, unsigned int cmd,
- unsigned long arg)
+ unsigned long arg)
{
drm_i915_irq_emit32_t req32;
drm_i915_irq_emit_t __user *request;
} drm_i915_getparam32_t;
static int compat_i915_getparam(struct file *file, unsigned int cmd,
- unsigned long arg)
+ unsigned long arg)
{
drm_i915_getparam32_t req32;
drm_i915_getparam_t __user *request;
} drm_i915_mem_alloc32_t;
static int compat_i915_alloc(struct file *file, unsigned int cmd,
- unsigned long arg)
+ unsigned long arg)
{
drm_i915_mem_alloc32_t req32;
drm_i915_mem_alloc_t __user *request;
*/
if ((pdev->device == 0x0525) && pdev->bus->self
- && (pdev->bus->self->vendor == 0x3388)
- && (pdev->bus->self->device == 0x0021) ) {
+ && (pdev->bus->self->vendor == 0x3388)
+ && (pdev->bus->self->device == 0x0021)) {
return 0;
}
static int compat_radeon_cp_stipple(struct file *file, unsigned int cmd,
unsigned long arg)
{
- drm_radeon_stipple32_t __user *argp = (void __user *) arg;
+ drm_radeon_stipple32_t __user *argp = (void __user *)arg;
drm_radeon_stipple_t __user *request;
u32 mask;
drm_radeon_tex_image32_t img32;
drm_radeon_tex_image_t __user *image;
- if (copy_from_user(&req32, (void __user *) arg, sizeof(req32)))
+ if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
return -EFAULT;
if (req32.image == 0)
return -EINVAL;
drm_radeon_vertex2_32_t req32;
drm_radeon_vertex2_t __user *request;
- if (copy_from_user(&req32, (void __user *) arg, sizeof(req32)))
+ if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
return -EFAULT;
request = compat_alloc_user_space(sizeof(*request));
drm_radeon_cmd_buffer32_t req32;
drm_radeon_cmd_buffer_t __user *request;
- if (copy_from_user(&req32, (void __user *) arg, sizeof(req32)))
+ if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
return -EFAULT;
request = compat_alloc_user_space(sizeof(*request));
drm_radeon_getparam32_t req32;
drm_radeon_getparam_t __user *request;
- if (copy_from_user(&req32, (void __user *) arg, sizeof(req32)))
+ if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
return -EFAULT;
request = compat_alloc_user_space(sizeof(*request));
drm_radeon_mem_alloc32_t req32;
drm_radeon_mem_alloc_t __user *request;
- if (copy_from_user(&req32, (void __user *) arg, sizeof(req32)))
+ if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
return -EFAULT;
request = compat_alloc_user_space(sizeof(*request));
drm_radeon_irq_emit32_t req32;
drm_radeon_irq_emit_t __user *request;
- if (copy_from_user(&req32, (void __user *) arg, sizeof(req32)))
+ if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
return -EFAULT;
request = compat_alloc_user_space(sizeof(*request));
drm_radeon_setparam32_t req32;
drm_radeon_setparam_t __user *request;
- if (copy_from_user(&req32, (void __user *) arg, sizeof(req32)))
+ if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
return -EFAULT;
request = compat_alloc_user_space(sizeof(*request));
;
}
-unsigned long sis_sman_mm_offset(void *private, void *ref)
+static unsigned long sis_sman_mm_offset(void *private, void *ref)
{
return ~((unsigned long)ref);
}
return 0;
}
-static int sis_drm_alloc(struct drm_device * dev, struct drm_file *file_priv,
+static int sis_drm_alloc(struct drm_device *dev, struct drm_file *file_priv,
void *data, int pool)
{
drm_sis_private_t *dev_priv = dev->dev_private;
return NULL;
}
-int
-sis_idle(struct drm_device *dev)
+int sis_idle(struct drm_device *dev)
{
drm_sis_private_t *dev_priv = dev->dev_private;
uint32_t idle_reg;
return -ENOMEM;
memset(vsg->pages, 0, sizeof(struct page *) * vsg->num_pages);
down_read(¤t->mm->mmap_sem);
- ret = get_user_pages(current, current->mm, (unsigned long) xfer->mem_addr,
- vsg->num_pages, (vsg->direction == DMA_FROM_DEVICE),
+ ret = get_user_pages(current, current->mm,
+ (unsigned long)xfer->mem_addr,
+ vsg->num_pages,
+ (vsg->direction == DMA_FROM_DEVICE),
0, vsg->pages, NULL);
up_read(¤t->mm->mmap_sem);
#else
drm_via_blitq_t *blitq = container_of(work, drm_via_blitq_t, wq);
#endif
- struct drm_device *dev = blitq->dev;
+ struct drm_device *dev = blitq->dev;
unsigned long irqsave;
drm_via_sg_info_t *cur_sg;
int cur_released;
struct drm_map *fb_map;
/* look up table parameters */
- struct ati_pcigart_info gart_info;
+ struct drm_ati_pcigart_info gart_info;
unsigned int lutPageSize;
struct drm_sman sman;
unsigned int signaled;
unsigned int error;
unsigned int sequence;
- unsigned int pad64;
+ unsigned int pad64;
uint64_t expand_pad[2]; /*Future expansion */
};
struct drm_mm_type_arg {
unsigned int mem_type;
- unsigned int lock_flags;
+ unsigned int lock_flags;
};
struct drm_mm_init_arg {
}
/* XXX: Emitting the counter should really be moved to part of the IRQ
- * emit. For now, do it in both places:
+ * emit. For now, do it in both places:
*/
void i915_emit_breadcrumb(struct drm_device *dev)
switch (param->param) {
case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
- dev_priv->use_mi_batchbuffer_start = param->value;
+ if (!IS_I965G(dev))
+ dev_priv->use_mi_batchbuffer_start = param->value;
break;
case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
dev_priv->tex_lru_log_granularity = param->value;
base = (u8 *) dev_priv->mmio_map->handle + e->offset;
switch (mmio->read_write) {
- case I915_MMIO_READ:
- if (!(e->flag & I915_MMIO_MAY_READ))
- return -EINVAL;
- for (i = 0; i < e->size / 4; i++)
- buf[i] = I915_READ(e->offset + i * 4);
- if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
- DRM_ERROR("DRM_COPY_TO_USER failed\n");
- return -EFAULT;
- }
- break;
-
- case I915_MMIO_WRITE:
- if (!(e->flag & I915_MMIO_MAY_WRITE))
- return -EINVAL;
- if(DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
- DRM_ERROR("DRM_COPY_TO_USER failed\n");
+ case I915_MMIO_READ:
+ if (!(e->flag & I915_MMIO_MAY_READ))
+ return -EINVAL;
+ for (i = 0; i < e->size / 4; i++)
+ buf[i] = I915_READ(e->offset + i * 4);
+ if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
+ DRM_ERROR("DRM_COPY_TO_USER failed\n");
+ return -EFAULT;
+ }
+ break;
+
+ case I915_MMIO_WRITE:
+ if (!(e->flag & I915_MMIO_MAY_WRITE))
+ return -EINVAL;
+ if(DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
+ DRM_ERROR("DRM_COPY_TO_USER failed\n");
return -EFAULT;
- }
- for (i = 0; i < e->size / 4; i++)
- I915_WRITE(e->offset + i * 4, buf[i]);
- break;
+ }
+ for (i = 0; i < e->size / 4; i++)
+ I915_WRITE(e->offset + i * 4, buf[i]);
+ break;
}
return 0;
}
unsigned int flag;
unsigned int offset;
unsigned int size;
-}drm_i915_mmio_entry_t;
+} drm_i915_mmio_entry_t;
typedef struct drm_i915_mmio {
unsigned int read_write:1;
#define MINIMAL_CLEANUP 0
#define FULL_CLEANUP 1
-static int mga_do_cleanup_dma(struct drm_device * dev, int full_cleanup);
+static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup);
/* ================================================================
* Engine control
int mga_driver_load(struct drm_device *dev, unsigned long flags)
{
- drm_mga_private_t * dev_priv;
+ drm_mga_private_t *dev_priv;
dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
if (!dev_priv)
static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
drm_mga_dma_bootstrap_t * dma_bs)
{
- drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private;
+ drm_mga_private_t *const dev_priv =
+ (drm_mga_private_t *)dev->dev_private;
unsigned int warp_size = mga_warp_microcode_size(dev_priv);
int err;
- unsigned offset;
+ unsigned offset;
const unsigned secondary_size = dma_bs->secondary_bin_count
* dma_bs->secondary_bin_size;
const unsigned agp_size = (dma_bs->agp_size << 20);
}
}
-
/* Allocate and bind AGP memory. */
agp_req.size = agp_size;
agp_req.type = 0;
- err = drm_agp_alloc( dev, & agp_req );
+ err = drm_agp_alloc(dev, &agp_req);
if (err) {
dev_priv->agp_size = 0;
DRM_ERROR("Unable to allocate %uMB AGP memory\n",
warp_size = PAGE_SIZE;
offset = 0;
- err = drm_addmap( dev, offset, warp_size,
- _DRM_AGP, _DRM_READ_ONLY, & dev_priv->warp );
+ err = drm_addmap(dev, offset, warp_size,
+ _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
if (err) {
DRM_ERROR("Unable to map WARP microcode: %d\n", err);
return err;
}
offset += warp_size;
- err = drm_addmap( dev, offset, dma_bs->primary_size,
- _DRM_AGP, _DRM_READ_ONLY, & dev_priv->primary );
+ err = drm_addmap(dev, offset, dma_bs->primary_size,
+ _DRM_AGP, _DRM_READ_ONLY, & dev_priv->primary);
if (err) {
DRM_ERROR("Unable to map primary DMA region: %d\n", err);
return err;
}
offset += dma_bs->primary_size;
- err = drm_addmap( dev, offset, secondary_size,
- _DRM_AGP, 0, & dev->agp_buffer_map );
+ err = drm_addmap(dev, offset, secondary_size,
+ _DRM_AGP, 0, & dev->agp_buffer_map);
if (err) {
DRM_ERROR("Unable to map secondary DMA region: %d\n", err);
return err;
}
- (void) memset( &req, 0, sizeof(req) );
+ (void)memset( &req, 0, sizeof(req) );
req.count = dma_bs->secondary_bin_count;
req.size = dma_bs->secondary_bin_size;
req.flags = _DRM_AGP_BUFFER;
req.agp_start = offset;
- err = drm_addbufs_agp( dev, & req );
+ err = drm_addbufs_agp(dev, &req);
if (err) {
DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
return err;
#endif
offset += secondary_size;
- err = drm_addmap( dev, offset, agp_size - offset,
- _DRM_AGP, 0, & dev_priv->agp_textures );
+ err = drm_addmap(dev, offset, agp_size - offset,
+ _DRM_AGP, 0, & dev_priv->agp_textures);
if (err) {
DRM_ERROR("Unable to map AGP texture region: %d\n", err);
return err;
static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
drm_mga_dma_bootstrap_t * dma_bs)
{
- drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private;
+ drm_mga_private_t *const dev_priv =
+ (drm_mga_private_t *) dev->dev_private;
unsigned int warp_size = mga_warp_microcode_size(dev_priv);
unsigned int primary_size;
unsigned int bin_count;
* alignment of the primary or secondary DMA buffers.
*/
- for ( primary_size = dma_bs->primary_size
- ; primary_size != 0
- ; primary_size >>= 1 ) {
+ for (primary_size = dma_bs->primary_size; primary_size != 0;
+ primary_size >>= 1 ) {
/* The proper alignment for this mapping is 0x04 */
err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
_DRM_READ_ONLY, &dev_priv->primary);
if (dev_priv->primary->size != dma_bs->primary_size) {
DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
dma_bs->primary_size,
- (unsigned) dev_priv->primary->size);
+ (unsigned)dev_priv->primary->size);
dma_bs->primary_size = dev_priv->primary->size;
}
- for ( bin_count = dma_bs->secondary_bin_count
- ; bin_count > 0
- ; bin_count-- ) {
- (void) memset( &req, 0, sizeof(req) );
+ for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
+ bin_count-- ) {
+ (void)memset(&req, 0, sizeof(req));
req.count = bin_count;
req.size = dma_bs->secondary_bin_size;
- err = drm_addbufs_pci( dev, & req );
+ err = drm_addbufs_pci(dev, &req);
if (!err) {
break;
}
}
-static int mga_do_dma_bootstrap(struct drm_device * dev,
- drm_mga_dma_bootstrap_t * dma_bs)
+static int mga_do_dma_bootstrap(struct drm_device *dev,
+ drm_mga_dma_bootstrap_t *dma_bs)
{
const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev);
int err;
- drm_mga_private_t * const dev_priv =
+ drm_mga_private_t *const dev_priv =
(drm_mga_private_t *) dev->dev_private;
/* The first steps are the same for both PCI and AGP based DMA. Map
* the cards MMIO registers and map a status page.
*/
- err = drm_addmap( dev, dev_priv->mmio_base, dev_priv->mmio_size,
- _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio );
+ err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
+ _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio);
if (err) {
DRM_ERROR("Unable to map MMIO region: %d\n", err);
return err;
}
- err = drm_addmap( dev, 0, SAREA_MAX, _DRM_SHM,
- _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
- & dev_priv->status );
+ err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
+ _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
+ & dev_priv->status);
if (err) {
DRM_ERROR("Unable to map status region: %d\n", err);
return err;
drm_mga_dma_bootstrap_t *bootstrap = data;
int err;
static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
- const drm_mga_private_t * const dev_priv =
+ const drm_mga_private_t *const dev_priv =
(drm_mga_private_t *) dev->dev_private;
return -EINVAL;
}
- if (! dev_priv->used_new_dma_init) {
+ if (!dev_priv->used_new_dma_init) {
dev_priv->dma_access = MGA_PAGPXFER;
dev_priv->wagp_enable = MGA_WAGP_ENABLE;
return -EINVAL;
}
dev->agp_buffer_token = init->buffers_offset;
- dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
+ dev->agp_buffer_map =
+ drm_core_findmap(dev, init->buffers_offset);
if (!dev->agp_buffer_map) {
DRM_ERROR("failed to find dma buffer region!\n");
return -EINVAL;
/* Init the primary DMA registers.
*/
MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
-#if 0
- MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
- MGA_PRIMPTREN1); /* DWGSYNC */
-#endif
dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
return 0;
}
-static int mga_do_cleanup_dma(struct drm_device * dev, int full_cleanup)
+static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup)
{
int err = 0;
DRM_DEBUG("\n");
memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
dev_priv->warp_pipe = 0;
- memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
+ memset(dev_priv->warp_pipe_phys, 0,
+ sizeof(dev_priv->warp_pipe_phys));
if (dev_priv->head != NULL) {
mga_freelist_cleanup(dev);
case MGA_INIT_DMA:
err = mga_do_init_dma(dev, init);
if (err) {
- (void) mga_do_cleanup_dma(dev, FULL_CLEANUP);
+ (void)mga_do_cleanup_dma(dev, FULL_CLEANUP);
}
return err;
case MGA_CLEANUP_DMA:
/* SOFTRAP interrupt */
if (status & MGA_SOFTRAPEN) {
const u32 prim_start = MGA_READ(MGA_PRIMADDRESS);
- const u32 prim_end = MGA_READ(MGA_PRIMEND);
+ const u32 prim_end = MGA_READ(MGA_PRIMEND);
MGA_WRITE(MGA_ICLEAR, MGA_SOFTRAPICLR);
/* In addition to clearing the interrupt-pending bit, we
* have to write to MGA_PRIMEND to re-start the DMA operation.
*/
- if ( (prim_start & ~0x03) != (prim_end & ~0x03) ) {
+ if ((prim_start & ~0x03) != (prim_end & ~0x03)) {
MGA_WRITE(MGA_PRIMEND, prim_end);
}
handled = 1;
}
- if ( handled ) {
+ if (handled)
return IRQ_HANDLED;
- }
return IRQ_NONE;
}
{
drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
- DRM_INIT_WAITQUEUE( &dev_priv->fence_queue );
+ DRM_INIT_WAITQUEUE(&dev_priv->fence_queue);
/* Turn on vertical blank interrupt and soft trap interrupt. */
MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN);
}
DMA_BLOCK(MGA_DMAPAD, 0x00000000,
MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1,
- MGA_YTOP, box->y1 * pitch,
- MGA_YBOT, (box->y2 - 1) * pitch);
+ MGA_YTOP, box->y1 * pitch, MGA_YBOT, (box->y2 - 1) * pitch);
ADVANCE_DMA();
}
DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
MGA_MACCESS, ctx->maccess,
- MGA_PLNWT, ctx->plnwt,
- MGA_DWGCTL, ctx->dwgctl);
+ MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
MGA_FOGCOL, ctx->fogcolor,
- MGA_WFLAG, ctx->wflag,
- MGA_ZORG, dev_priv->depth_offset);
+ MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
DMA_BLOCK(MGA_FCOL, ctx->fcol,
MGA_DMAPAD, 0x00000000,
- MGA_DMAPAD, 0x00000000,
- MGA_DMAPAD, 0x00000000);
+ MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
ADVANCE_DMA();
}
drm_local_map_t *cce_ring;
drm_local_map_t *ring_rptr;
drm_local_map_t *agp_textures;
- struct ati_pcigart_info gart_info;
+ struct drm_ati_pcigart_info gart_info;
} drm_r128_private_t;
typedef struct drm_r128_buf_priv {
int irq_enabled;
struct radeon_surface surfaces[RADEON_MAX_SURFACES];
- struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
+ struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
unsigned long pcigart_offset;
unsigned int pcigart_offset_set;
- struct ati_pcigart_info gart_info;
+ struct drm_ati_pcigart_info gart_info;
u32 scratch_ages[5];
extern int r300_do_cp_cmdbuf(struct drm_device *dev,
struct drm_file *file_priv,
- drm_radeon_kcmd_buffer_t* cmdbuf);
+ drm_radeon_kcmd_buffer_t *cmdbuf);
/* Flags for stats.boxes
*/
}
static int radeon_driver_vblank_do_wait(struct drm_device * dev,
- unsigned int *sequence,
- int crtc)
+ unsigned int *sequence, int crtc)
{
drm_radeon_private_t *dev_priv =
(drm_radeon_private_t *) dev->dev_private;
*
* DRM infrastructure takes care of reclaiming dma buffers.
*/
-void radeon_driver_preclose(struct drm_device * dev,
+void radeon_driver_preclose(struct drm_device *dev,
struct drm_file *file_priv)
{
if (dev->dev_private) {
}
}
-void radeon_driver_lastclose(struct drm_device * dev)
+void radeon_driver_lastclose(struct drm_device *dev)
{
if (dev->dev_private) {
drm_radeon_private_t *dev_priv = dev->dev_private;
radeon_do_release(dev);
}
-int radeon_driver_open(struct drm_device * dev, struct drm_file *file_priv)
+int radeon_driver_open(struct drm_device *dev, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_driver_file_fields *radeon_priv;
return 0;
}
-void radeon_driver_postclose(struct drm_device * dev, struct drm_file *file_priv)
+void radeon_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
{
struct drm_radeon_driver_file_fields *radeon_priv =
file_priv->driver_priv;
unsigned int cur = dev_priv->current_dma_page;
unsigned int rest = SAVAGE_DMA_PAGE_SIZE -
dev_priv->dma_pages[cur].used;
- unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE-1) /
+ unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) /
SAVAGE_DMA_PAGE_SIZE;
uint32_t *dma_ptr;
unsigned int i;
if (cur + nr_pages < dev_priv->nr_dma_pages) {
dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle +
- cur*SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
+ cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
if (n < rest)
rest = n;
dev_priv->dma_pages[cur].used += rest;
} else {
dev_priv->dma_flush(dev_priv);
nr_pages =
- (n + SAVAGE_DMA_PAGE_SIZE-1) / SAVAGE_DMA_PAGE_SIZE;
+ (n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE;
for (i = cur; i < dev_priv->nr_dma_pages; ++i) {
dev_priv->dma_pages[i].age = dev_priv->last_dma_age;
dev_priv->dma_pages[i].used = 0;
uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle +
cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
dev_priv->dma_pages[cur].used += pad;
- while(pad != 0) {
+ while (pad != 0) {
*dma_ptr++ = BCI_CMD_WAIT;
pad--;
}
dev_priv->mtrr[0].handle =
drm_mtrr_add(dev_priv->mtrr[0].base,
dev_priv->mtrr[0].size, DRM_MTRR_WC);
- dev_priv->mtrr[1].base = fb_base+0x02000000;
+ dev_priv->mtrr[1].base = fb_base + 0x02000000;
dev_priv->mtrr[1].size = 0x02000000;
dev_priv->mtrr[1].handle =
drm_mtrr_add(dev_priv->mtrr[1].base,
dev_priv->mtrr[1].size, DRM_MTRR_WC);
- dev_priv->mtrr[2].base = fb_base+0x04000000;
+ dev_priv->mtrr[2].base = fb_base + 0x04000000;
dev_priv->mtrr[2].size = 0x04000000;
dev_priv->mtrr[2].handle =
drm_mtrr_add(dev_priv->mtrr[2].base,
depth_tile_format = SAVAGE_BD_TILE_DEST;
}
front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8);
- back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8);
+ back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8);
depth_stride =
dev_priv->depth_pitch / (dev_priv->depth_bpp / 8);
return -ENOMEM;
}
- if (savage_dma_init(dev_priv) < 0) {
+ if (savage_dma_init(dev_priv) < 0) {
DRM_ERROR("could not initialize command DMA\n");
savage_do_cleanup_bci(dev);
return -ENOMEM;
* - event counter wrapped since the event was emitted or
* - the hardware has advanced up to or over the event to wait for.
*/
- if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e) )
+ if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e))
return 0;
else
return dev_priv->wait_evnt(dev_priv, event_e);
if (!dma->buflist)
return;
- /*i830_flush_queue(dev);*/
-
for (i = 0; i < dma->buf_count; i++) {
struct drm_buf *buf = dma->buflist[i];
drm_savage_buf_priv_t *buf_priv = buf->dev_private;
const struct drm_clip_rect *pbox)
{
uint32_t scstart = dev_priv->state.s3d.new_scstart;
- uint32_t scend = dev_priv->state.s3d.new_scend;
+ uint32_t scend = dev_priv->state.s3d.new_scend;
scstart = (scstart & ~SAVAGE_SCISSOR_MASK_S3D) |
((uint32_t)pbox->x1 & 0x000007ff) |
(((uint32_t)pbox->y1 << 16) & 0x07ff0000);
- scend = (scend & ~SAVAGE_SCISSOR_MASK_S3D) |
- (((uint32_t)pbox->x2-1) & 0x000007ff) |
- ((((uint32_t)pbox->y2-1) << 16) & 0x07ff0000);
+ scend = (scend & ~SAVAGE_SCISSOR_MASK_S3D) |
+ (((uint32_t)pbox->x2 - 1) & 0x000007ff) |
+ ((((uint32_t)pbox->y2 - 1) << 16) & 0x07ff0000);
if (scstart != dev_priv->state.s3d.scstart ||
scend != dev_priv->state.s3d.scend) {
DMA_LOCALS;
BEGIN_DMA(4);
- DMA_WRITE(BCI_CMD_WAIT|BCI_CMD_WAIT_3D);
+ DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D);
DMA_SET_REGISTERS(SAVAGE_SCSTART_S3D, 2);
DMA_WRITE(scstart);
DMA_WRITE(scend);
dev_priv->state.s3d.scstart = scstart;
- dev_priv->state.s3d.scend = scend;
+ dev_priv->state.s3d.scend = scend;
dev_priv->waiting = 1;
DMA_COMMIT();
}
((uint32_t)pbox->x1 & 0x000007ff) |
(((uint32_t)pbox->y1 << 12) & 0x00fff000);
drawctrl1 = (drawctrl1 & ~SAVAGE_SCISSOR_MASK_S4) |
- (((uint32_t)pbox->x2-1) & 0x000007ff) |
- ((((uint32_t)pbox->y2-1) << 12) & 0x00fff000);
+ (((uint32_t)pbox->x2 - 1) & 0x000007ff) |
+ ((((uint32_t)pbox->y2 - 1) << 12) & 0x00fff000);
if (drawctrl0 != dev_priv->state.s4.drawctrl0 ||
drawctrl1 != dev_priv->state.s4.drawctrl1) {
DMA_LOCALS;
BEGIN_DMA(4);
- DMA_WRITE(BCI_CMD_WAIT|BCI_CMD_WAIT_3D);
+ DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D);
DMA_SET_REGISTERS(SAVAGE_DRAWCTRL0_S4, 2);
DMA_WRITE(drawctrl0);
DMA_WRITE(drawctrl1);
}
if (!(addr & 1)) { /* local */
addr &= ~7;
- if (addr < dev_priv->texture_offset ||
- addr >= dev_priv->texture_offset+dev_priv->texture_size) {
+ if (addr < dev_priv->texture_offset ||
+ addr >= dev_priv->texture_offset + dev_priv->texture_size) {
DRM_ERROR
("bad texAddr%d %08x (local addr out of range)\n",
unit, addr);
}
#define SAVE_STATE(reg,where) \
- if(start <= reg && start+count > reg) \
+ if(start <= reg && start + count > reg) \
dev_priv->state.where = regs[reg - start]
#define SAVE_STATE_MASK(reg,where,mask) do { \
- if(start <= reg && start+count > reg) { \
+ if(start <= reg && start + count > reg) { \
uint32_t tmp; \
tmp = regs[reg - start]; \
dev_priv->state.where = (tmp & (mask)) | \
const uint32_t *regs)
{
if (start < SAVAGE_TEXPALADDR_S3D ||
- start+count-1 > SAVAGE_DESTTEXRWWATERMARK_S3D) {
+ start + count - 1 > SAVAGE_DESTTEXRWWATERMARK_S3D) {
DRM_ERROR("invalid register range (0x%04x-0x%04x)\n",
- start, start+count-1);
+ start, start + count - 1);
return -EINVAL;
}
/* if any texture regs were changed ... */
if (start <= SAVAGE_TEXCTRL_S3D &&
- start+count > SAVAGE_TEXPALADDR_S3D) {
+ start + count > SAVAGE_TEXPALADDR_S3D) {
/* ... check texture state */
SAVE_STATE(SAVAGE_TEXCTRL_S3D, s3d.texctrl);
SAVE_STATE(SAVAGE_TEXADDR_S3D, s3d.texaddr);
int ret = 0;
if (start < SAVAGE_DRAWLOCALCTRL_S4 ||
- start+count-1 > SAVAGE_TEXBLENDCOLOR_S4) {
+ start + count - 1 > SAVAGE_TEXBLENDCOLOR_S4) {
DRM_ERROR("invalid register range (0x%04x-0x%04x)\n",
- start, start+count-1);
+ start, start + count - 1);
return -EINVAL;
}
return ret;
/* scissor regs are emitted in savage_dispatch_draw */
if (start < SAVAGE_SCSTART_S3D) {
- if (start+count > SAVAGE_SCEND_S3D+1)
- count2 = count - (SAVAGE_SCEND_S3D+1 - start);
- if (start+count > SAVAGE_SCSTART_S3D)
+ if (start + count > SAVAGE_SCEND_S3D + 1)
+ count2 = count - (SAVAGE_SCEND_S3D + 1 - start);
+ if (start + count > SAVAGE_SCSTART_S3D)
count = SAVAGE_SCSTART_S3D - start;
} else if (start <= SAVAGE_SCEND_S3D) {
- if (start+count > SAVAGE_SCEND_S3D+1) {
- count -= SAVAGE_SCEND_S3D+1 - start;
- start = SAVAGE_SCEND_S3D+1;
+ if (start + count > SAVAGE_SCEND_S3D + 1) {
+ count -= SAVAGE_SCEND_S3D + 1 - start;
+ start = SAVAGE_SCEND_S3D + 1;
} else
return 0;
}
return ret;
/* scissor regs are emitted in savage_dispatch_draw */
if (start < SAVAGE_DRAWCTRL0_S4) {
- if (start+count > SAVAGE_DRAWCTRL1_S4+1)
+ if (start + count > SAVAGE_DRAWCTRL1_S4 + 1)
count2 = count -
(SAVAGE_DRAWCTRL1_S4 + 1 - start);
- if (start+count > SAVAGE_DRAWCTRL0_S4)
+ if (start + count > SAVAGE_DRAWCTRL0_S4)
count = SAVAGE_DRAWCTRL0_S4 - start;
} else if (start <= SAVAGE_DRAWCTRL1_S4) {
- if (start+count > SAVAGE_DRAWCTRL1_S4+1) {
- count -= SAVAGE_DRAWCTRL1_S4+1 - start;
- start = SAVAGE_DRAWCTRL1_S4+1;
+ if (start + count > SAVAGE_DRAWCTRL1_S4 + 1) {
+ count -= SAVAGE_DRAWCTRL1_S4 + 1 - start;
+ start = SAVAGE_DRAWCTRL1_S4 + 1;
} else
return 0;
}
}
- bci_size = count + (count+254)/255 + count2 + (count2+254)/255;
+ bci_size = count + (count + 254) / 255 + count2 + (count2 + 254) / 255;
if (cmd_header->state.global) {
- BEGIN_DMA(bci_size+1);
+ BEGIN_DMA(bci_size + 1);
DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D);
dev_priv->waiting = 1;
} else {
BCI_LOCALS;
if (!dmabuf) {
- DRM_ERROR("called without dma buffers!\n");
- return -EINVAL;
+ DRM_ERROR("called without dma buffers!\n");
+ return -EINVAL;
}
if (!n)
}
}
- if (start + n > dmabuf->total/32) {
+ if (start + n > dmabuf->total / 32) {
DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n",
- start, start + n - 1, dmabuf->total/32);
+ start, start + n - 1, dmabuf->total / 32);
return -EINVAL;
}
/* Need to reorder indices for correct flat
* shading while preserving the clock sense
* for correct culling. Only on Savage3D. */
- int reorder[3] = {-1, -1, -1};
- reorder[start%3] = 2;
+ int reorder[3] = { -1, -1, -1 };
+ reorder[start % 3] = 2;
- BEGIN_BCI((count+1+1)/2);
- BCI_DRAW_INDICES_S3D(count, prim, start+2);
+ BEGIN_BCI((count + 1 + 1) / 2);
+ BCI_DRAW_INDICES_S3D(count, prim, start + 2);
- for (i = start+1; i+1 < start+count; i += 2)
+ for (i = start + 1; i + 1 < start + count; i += 2)
BCI_WRITE((i + reorder[i % 3]) |
((i + 1 +
reorder[(i + 1) % 3]) << 16));
- if (i < start+count)
- BCI_WRITE(i + reorder[i%3]);
+ if (i < start + count)
+ BCI_WRITE(i + reorder[i % 3]);
} else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
- BEGIN_BCI((count+1+1)/2);
+ BEGIN_BCI((count + 1 + 1) / 2);
BCI_DRAW_INDICES_S3D(count, prim, start);
- for (i = start+1; i+1 < start+count; i += 2)
- BCI_WRITE(i | ((i+1) << 16));
- if (i < start+count)
+ for (i = start + 1; i + 1 < start + count; i += 2)
+ BCI_WRITE(i | ((i + 1) << 16));
+ if (i < start + count)
BCI_WRITE(i);
} else {
- BEGIN_BCI((count+2+1)/2);
+ BEGIN_BCI((count + 2 + 1) / 2);
BCI_DRAW_INDICES_S4(count, prim, skip);
- for (i = start; i+1 < start+count; i += 2)
- BCI_WRITE(i | ((i+1) << 16));
- if (i < start+count)
+ for (i = start; i + 1 < start + count; i += 2)
+ BCI_WRITE(i | ((i + 1) << 16));
+ if (i < start + count)
BCI_WRITE(i);
}
return -EINVAL;
}
- if (start + n > vb_size / (vb_stride*4)) {
+ if (start + n > vb_size / (vb_stride * 4)) {
DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n",
- start, start + n - 1, vb_size / (vb_stride*4));
+ start, start + n - 1, vb_size / (vb_stride * 4));
return -EINVAL;
}
/* Need to reorder vertices for correct flat
* shading while preserving the clock sense
* for correct culling. Only on Savage3D. */
- int reorder[3] = {-1, -1, -1};
- reorder[start%3] = 2;
+ int reorder[3] = { -1, -1, -1 };
+ reorder[start % 3] = 2;
- BEGIN_DMA(count*vtx_size+1);
+ BEGIN_DMA(count * vtx_size + 1);
DMA_DRAW_PRIMITIVE(count, prim, skip);
- for (i = start; i < start+count; ++i) {
+ for (i = start; i < start + count; ++i) {
unsigned int j = i + reorder[i % 3];
- DMA_COPY(&vtxbuf[vb_stride*j], vtx_size);
+ DMA_COPY(&vtxbuf[vb_stride * j], vtx_size);
}
DMA_COMMIT();
} else {
- BEGIN_DMA(count*vtx_size+1);
+ BEGIN_DMA(count * vtx_size + 1);
DMA_DRAW_PRIMITIVE(count, prim, skip);
if (vb_stride == vtx_size) {
- DMA_COPY(&vtxbuf[vb_stride*start],
- vtx_size*count);
+ DMA_COPY(&vtxbuf[vb_stride * start],
+ vtx_size * count);
} else {
- for (i = start; i < start+count; ++i) {
- DMA_COPY(&vtxbuf[vb_stride*i],
+ for (i = start; i < start + count; ++i) {
+ DMA_COPY(&vtxbuf[vb_stride * i],
vtx_size);
}
}
BCI_LOCALS;
if (!dmabuf) {
- DRM_ERROR("called without dma buffers!\n");
- return -EINVAL;
+ DRM_ERROR("called without dma buffers!\n");
+ return -EINVAL;
}
if (!n)
/* check indices */
for (i = 0; i < count; ++i) {
- if (idx[i] > dmabuf->total/32) {
+ if (idx[i] > dmabuf->total / 32) {
DRM_ERROR("idx[%u]=%u out of range (0-%u)\n",
- i, idx[i], dmabuf->total/32);
+ i, idx[i], dmabuf->total / 32);
return -EINVAL;
}
}
/* Need to reorder indices for correct flat
* shading while preserving the clock sense
* for correct culling. Only on Savage3D. */
- int reorder[3] = {2, -1, -1};
+ int reorder[3] = { 2, -1, -1 };
- BEGIN_BCI((count+1+1)/2);
+ BEGIN_BCI((count + 1 + 1) / 2);
BCI_DRAW_INDICES_S3D(count, prim, idx[2]);
- for (i = 1; i+1 < count; i += 2)
+ for (i = 1; i + 1 < count; i += 2)
BCI_WRITE(idx[i + reorder[i % 3]] |
(idx[i + 1 +
reorder[(i + 1) % 3]] << 16));
if (i < count)
- BCI_WRITE(idx[i + reorder[i%3]]);
+ BCI_WRITE(idx[i + reorder[i % 3]]);
} else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
- BEGIN_BCI((count+1+1)/2);
+ BEGIN_BCI((count + 1 + 1) / 2);
BCI_DRAW_INDICES_S3D(count, prim, idx[0]);
- for (i = 1; i+1 < count; i += 2)
- BCI_WRITE(idx[i] | (idx[i+1] << 16));
+ for (i = 1; i + 1 < count; i += 2)
+ BCI_WRITE(idx[i] | (idx[i + 1] << 16));
if (i < count)
BCI_WRITE(idx[i]);
} else {
- BEGIN_BCI((count+2+1)/2);
+ BEGIN_BCI((count + 2 + 1) / 2);
BCI_DRAW_INDICES_S4(count, prim, skip);
- for (i = 0; i+1 < count; i += 2)
- BCI_WRITE(idx[i] | (idx[i+1] << 16));
+ for (i = 0; i + 1 < count; i += 2)
+ BCI_WRITE(idx[i] | (idx[i + 1] << 16));
if (i < count)
BCI_WRITE(idx[i]);
}
/* Check indices */
for (i = 0; i < count; ++i) {
- if (idx[i] > vb_size / (vb_stride*4)) {
+ if (idx[i] > vb_size / (vb_stride * 4)) {
DRM_ERROR("idx[%u]=%u out of range (0-%u)\n",
- i, idx[i], vb_size / (vb_stride*4));
+ i, idx[i], vb_size / (vb_stride * 4));
return -EINVAL;
}
}
/* Need to reorder vertices for correct flat
* shading while preserving the clock sense
* for correct culling. Only on Savage3D. */
- int reorder[3] = {2, -1, -1};
+ int reorder[3] = { 2, -1, -1 };
- BEGIN_DMA(count*vtx_size+1);
+ BEGIN_DMA(count * vtx_size + 1);
DMA_DRAW_PRIMITIVE(count, prim, skip);
for (i = 0; i < count; ++i) {
unsigned int j = idx[i + reorder[i % 3]];
- DMA_COPY(&vtxbuf[vb_stride*j], vtx_size);
+ DMA_COPY(&vtxbuf[vb_stride * j], vtx_size);
}
DMA_COMMIT();
} else {
- BEGIN_DMA(count*vtx_size+1);
+ BEGIN_DMA(count * vtx_size + 1);
DMA_DRAW_PRIMITIVE(count, prim, skip);
for (i = 0; i < count; ++i) {
unsigned int j = idx[i];
- DMA_COPY(&vtxbuf[vb_stride*j], vtx_size);
+ DMA_COPY(&vtxbuf[vb_stride * j], vtx_size);
}
DMA_COMMIT();
x = boxes[i].x1, y = boxes[i].y1;
w = boxes[i].x2 - boxes[i].x1;
h = boxes[i].y2 - boxes[i].y1;
- BEGIN_DMA(nbufs*6);
+ BEGIN_DMA(nbufs * 6);
for (buf = SAVAGE_FRONT; buf <= SAVAGE_DEPTH; buf <<= 1) {
if (!(flags & buf))
continue;
DMA_WRITE(clear_cmd);
- switch(buf) {
+ switch (buf) {
case SAVAGE_FRONT:
DMA_WRITE(dev_priv->front_offset);
DMA_WRITE(dev_priv->front_bd);
DMA_WRITE(dev_priv->back_bd);
DMA_WRITE(BCI_X_Y(boxes[i].x1, boxes[i].y1));
DMA_WRITE(BCI_X_Y(boxes[i].x1, boxes[i].y1));
- DMA_WRITE(BCI_W_H(boxes[i].x2-boxes[i].x1,
- boxes[i].y2-boxes[i].y1));
+ DMA_WRITE(BCI_W_H(boxes[i].x2 - boxes[i].x1,
+ boxes[i].y2 - boxes[i].y1));
DMA_COMMIT();
}
if (cmdbuf->dma_idx > dma->buf_count) {
DRM_ERROR
("vertex buffer index %u out of range (0-%u)\n",
- cmdbuf->dma_idx, dma->buf_count-1);
+ cmdbuf->dma_idx, dma->buf_count - 1);
return -EINVAL;
}
dmabuf = dma->buflist[cmdbuf->dma_idx];
case SAVAGE_CMD_DMA_PRIM:
case SAVAGE_CMD_VB_PRIM:
if (!first_draw_cmd)
- first_draw_cmd = cmdbuf->cmd_addr-1;
+ first_draw_cmd = cmdbuf->cmd_addr - 1;
cmdbuf->cmd_addr += j;
i += j;
break;
default:
if (first_draw_cmd) {
- ret = savage_dispatch_draw (
+ ret = savage_dispatch_draw(
dev_priv, first_draw_cmd,
- cmdbuf->cmd_addr-1,
+ cmdbuf->cmd_addr - 1,
dmabuf, cmdbuf->vb_addr,
cmdbuf->vb_size,
cmdbuf->vb_stride,
}
if (first_draw_cmd) {
- ret = savage_dispatch_draw (
+ ret = savage_dispatch_draw(
dev_priv, first_draw_cmd, cmdbuf->cmd_addr, dmabuf,
cmdbuf->vb_addr, cmdbuf->vb_size, cmdbuf->vb_stride,
cmdbuf->nbox, cmdbuf->box_addr);
#endif
-
-
extern struct drm_ioctl_desc sis_ioctls[];
extern int sis_max_ioctl;
#define HC_HAGPBpID_STOP 0x00000002
#define HC_HAGPBpH_MASK 0x00ffffff
-
#define VIA_VIDEO_HEADER5 0xFE040000
#define VIA_VIDEO_HEADER6 0xFE050000
#define VIA_VIDEO_HEADER7 0xFE060000
*vb++ = (w2); \
dev_priv->dma_low += 8;
-static void via_cmdbuf_start(drm_via_private_t * dev_priv);
-static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
-static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
-static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
-static int via_wait_idle(drm_via_private_t * dev_priv);
+static void via_cmdbuf_start(drm_via_private_t *dev_priv);
+static void via_cmdbuf_pause(drm_via_private_t *dev_priv);
+static void via_cmdbuf_reset(drm_via_private_t *dev_priv);
+static void via_cmdbuf_rewind(drm_via_private_t *dev_priv);
+static int via_wait_idle(drm_via_private_t *dev_priv);
static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);
if (count-- == 0) {
DRM_ERROR
("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
- hw_addr, cur_addr, next_addr);
+ hw_addr, cur_addr, next_addr);
return -1;
}
} while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
-static int via_wait_idle(drm_via_private_t * dev_priv)
+static int via_wait_idle(drm_via_private_t *dev_priv)
{
int count = 10000000;
return count;
}
-static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
+static uint32_t *via_align_cmd(drm_via_private_t *dev_priv, uint32_t cmd_type,
uint32_t addr, uint32_t *cmd_addr_hi,
uint32_t *cmd_addr_lo, int skip_wait)
{
uint32_t qw_pad_count;
if (!skip_wait)
- via_cmdbuf_wait(dev_priv, 2*CMDBUF_ALIGNMENT_SIZE);
+ via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
vb = via_get_dma(dev_priv);
- VIA_OUT_RING_QW( HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
- (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
+ VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
+ (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
+
agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
via_cmdbuf_wait(dev_priv, qwords + 2);
vb = via_get_dma(dev_priv);
- VIA_OUT_RING_QW( HC_HEADER2, HC_ParaType_NotTex << 16);
- via_align_buffer(dev_priv,vb,qwords);
+ VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16);
+ via_align_buffer(dev_priv, vb, qwords);
}
static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
volatile uint32_t *last_pause_ptr;
agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
- via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
+ via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
&jump_addr_lo, 0);
dev_priv->dma_wrap = dev_priv->dma_low;
via_dummy_bitblt(dev_priv);
via_dummy_bitblt(dev_priv);
- last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
+ last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
&pause_addr_lo, 0) -1;
- via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
+ via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
&pause_addr_lo, 0);
*last_pause_ptr = pause_addr_lo;
- via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0);
+ via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0);
}
-
static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
{
via_cmdbuf_jump(dev_priv);
uint32_t pause_addr_lo, pause_addr_hi;
via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
- via_hook_segment( dev_priv, pause_addr_hi, pause_addr_lo, 0);
+ via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
}
count = 1000000;
tmp_size = d_siz->size;
- switch(d_siz->func) {
+ switch (d_siz->func) {
case VIA_CMDBUF_SPACE:
while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz->size)
&& count--) {
#define VIA_IRQ_FLAGS_MASK 0xF0000000
-enum drm_via_irqs{
+enum drm_via_irqs {
drm_via_irq_hqv0 = 0,
drm_via_irq_hqv1,
drm_via_irq_dma0_dd,
drm_via_irq_num
};
-struct drm_via_wait_irq_request{
+struct drm_via_wait_irq_request {
unsigned irq;
via_irq_seq_type_t type;
uint32_t sequence;
uint32_t fb_stride;
unsigned char *mem_addr;
- uint32_t mem_stride;
+ uint32_t mem_stride;
- uint32_t flags;
+ uint32_t flags;
int to_fb;
drm_via_blitsync_t sync;
{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
};
-static int via_num_pro_group_a =
- sizeof(via_pro_group_a_irqs)/sizeof(maskarray_t);
+static int via_num_pro_group_a = ARRAY_SIZE(via_pro_group_a_irqs);
static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};
static maskarray_t via_unichrome_irqs[] = {
{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}
};
-static int via_num_unichrome = sizeof(via_unichrome_irqs)/sizeof(maskarray_t);
+static int via_num_unichrome = ARRAY_SIZE(via_unichrome_irqs);
static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
static unsigned time_diff(struct timeval *now,struct timeval *then)
{
- return (now->tv_usec >= then->tv_usec) ?
- now->tv_usec - then->tv_usec :
- 1000000 - (then->tv_usec - now->tv_usec);
+ return (now->tv_usec >= then->tv_usec) ?
+ now->tv_usec - then->tv_usec :
+ 1000000 - (then->tv_usec - now->tv_usec);
}
irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
}
if (!(atomic_read(&dev->vbl_received) & 0xFF)) {
DRM_DEBUG("US per vblank is: %u\n",
- dev_priv->usec_per_vblank);
+ dev_priv->usec_per_vblank);
}
DRM_WAKEUP(&dev->vbl_queue);
drm_vbl_send_signals(dev);
handled = 1;
}
- for (i=0; i<dev_priv->num_irqs; ++i) {
+ for (i = 0; i < dev_priv->num_irqs; ++i) {
if (status & cur_irq->pending_mask) {
- atomic_inc( &cur_irq->irq_received );
- DRM_WAKEUP( &cur_irq->irq_queue );
+ atomic_inc(&cur_irq->irq_received);
+ DRM_WAKEUP(&cur_irq->irq_queue);
handled = 1;
#ifdef VIA_HAVE_DMABLIT
if (dev_priv->irq_map[drm_via_irq_dma0_td] == i) {
return -EINVAL;
}
- if (irq >= drm_via_irq_num ) {
+ if (irq >= drm_via_irq_num) {
DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__,
irq);
return -EINVAL;
dev_priv->irq_map = via_irqmap_unichrome;
}
- for(i=0; i < dev_priv->num_irqs; ++i) {
+ for (i = 0; i < dev_priv->num_irqs; ++i) {
atomic_set(&cur_irq->irq_received, 0);
cur_irq->enable_mask = dev_priv->irq_masks[i][0];
cur_irq->pending_mask = dev_priv->irq_masks[i][1];
- DRM_INIT_WAITQUEUE( &cur_irq->irq_queue );
+ DRM_INIT_WAITQUEUE(&cur_irq->irq_queue);
dev_priv->irq_enable_mask |= cur_irq->enable_mask;
dev_priv->irq_pending_mask |= cur_irq->pending_mask;
cur_irq++;
* Partially stolen from drm_memory.h
*/
-static __inline__ drm_local_map_t *via_drm_lookup_agp_map(drm_via_state_t * seq,
+static __inline__ drm_local_map_t *via_drm_lookup_agp_map(drm_via_state_t *seq,
unsigned long offset,
unsigned long size,
- struct drm_device * dev)
+ struct drm_device *dev)
{
#ifdef __linux__
struct drm_map_list *r_list;
tex_address
} drm_via_sequence_t;
-
-
typedef struct {
unsigned texture;
uint32_t z_addr;
uint32_t tex_level_lo[2];
uint32_t tex_level_hi[2];
uint32_t tex_palette_size[2];
- uint32_t tex_npot[2];
+ uint32_t tex_npot[2];
drm_via_sequence_t unfinished;
int agp_texture;
int multitex;
const uint32_t *buf_start;
} drm_via_state_t;
-extern int via_verify_command_stream(const uint32_t * buf, unsigned int size,
+extern int via_verify_command_stream(const uint32_t *buf, unsigned int size,
struct drm_device *dev, int agp);
-extern int via_parse_command_stream(struct drm_device *dev, const uint32_t * buf,
+extern int via_parse_command_stream(struct drm_device *dev, const uint32_t *buf,
unsigned int size);
#endif
projects / platform / upstream / libdrm.git / commitdiff