Overwrite bootmode selected via boot mode pins to tell SPL what should
be the next boot device.
+config ZYNQ_SDHCI_MAX_FREQ
+ default 200000000
+
config SPL_ZYNQMP_ALT_BOOTMODE
hex
default 0x0 if JTAG_MODE
Add register writes to boot.bin format (max 256 pairs).
Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
+config ZYNQ_SDHCI_MAX_FREQ
+ default 52000000
+
endif
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=52000000
CONFIG_ZYNQMP_USB=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
CONFIG_DEBUG_UART=y
help
Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform
+config ZYNQ_SDHCI_MAX_FREQ
+ int "Set the maximum frequency of the controller"
+ depends on MMC_SDHCI_ZYNQ
+ help
+ Set the maximum frequency of the controller.
+
config MMC_SUNXI
bool "Allwinner sunxi SD/MMC Host Controller support"
depends on ARCH_SUNXI && !UART0_PORT_F
#if defined(CONFIG_MMC_SDHCI_ZYNQ)
# define CONFIG_SUPPORT_EMMC_BOOT
-# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
-# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000
-# endif
#endif
#ifdef CONFIG_NAND_ARASAN
#ifndef __CONFIG_ZYNQMP_EP_H
#define __CONFIG_ZYNQMP_EP_H
-#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9)
#define CONFIG_ZYNQ_EEPROM
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
#define CONFIG_MTD_DEVICE
#endif
-/* MMC */
-#if defined(CONFIG_MMC_SDHCI_ZYNQ)
-# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
-#endif
-
#ifdef CONFIG_USB_EHCI_ZYNQ
# define CONFIG_EHCI_IS_TDI