s390/barrier: remove unnecessary serialization in atomics and bitops
authorMartin Schwidefsky <schwidefsky@de.ibm.com>
Mon, 28 Sep 2015 13:27:26 +0000 (15:27 +0200)
committerMartin Schwidefsky <schwidefsky@de.ibm.com>
Wed, 14 Oct 2015 12:32:07 +0000 (14:32 +0200)
The principles of operation states reads are in order, writes are in
order, writes can be reordered after reads, but no reads can be
reordered after writes.

The atomic and bitops variantes for z196 use the interlocked-access
facility instructions with a memory barrier before and after the
instruction. Because of the memory ordering the first barrier is
unnecessary and can be removed.

Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
arch/s390/include/asm/atomic.h
arch/s390/include/asm/bitops.h

index 117fa5c..911064a 100644 (file)
@@ -36,7 +36,6 @@
                                                                        \
        typecheck(atomic_t *, ptr);                                     \
        asm volatile(                                                   \
-               __barrier                                               \
                op_string "     %0,%2,%1\n"                             \
                __barrier                                               \
                : "=d" (old_val), "+Q" ((ptr)->counter)                 \
@@ -180,7 +179,6 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
                                                                        \
        typecheck(atomic64_t *, ptr);                                   \
        asm volatile(                                                   \
-               __barrier                                               \
                op_string "     %0,%2,%1\n"                             \
                __barrier                                               \
                : "=d" (old_val), "+Q" ((ptr)->counter)                 \
index 66a1cff..47bd087 100644 (file)
@@ -64,7 +64,6 @@
                                                                \
        typecheck(unsigned long *, (__addr));                   \
        asm volatile(                                           \
-               __barrier                                       \
                __op_string "   %0,%2,%1\n"                     \
                __barrier                                       \
                : "=d" (__old), "+Q" (*(__addr))                \