sunxi: H616: add DRAM type selection
authorMikhail Kalashnikov <iuncuim@gmail.com>
Wed, 7 Jun 2023 00:07:44 +0000 (01:07 +0100)
committerAndre Przywara <andre.przywara@arm.com>
Thu, 20 Jul 2023 23:54:13 +0000 (00:54 +0100)
Allwinner H616 SoC supports several types of DRAM memory. To further
integrate other types of memory, we need to add this delimitation.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
arch/arm/mach-sunxi/Kconfig
arch/arm/mach-sunxi/dram_timings/Makefile
configs/orangepi_zero2_defconfig
configs/x96_mate_defconfig

index e0b1bde..b38dce6 100644 (file)
@@ -431,7 +431,7 @@ config ARM_BOOT_HOOK_RMR
        This allows both the SPL and the U-Boot proper to be entered in
        either mode and switch to AArch64 if needed.
 
-if SUNXI_DRAM_DW || DRAM_SUN50I_H6
+if SUNXI_DRAM_DW || DRAM_SUN50I_H6 || DRAM_SUN50I_H616
 config SUNXI_DRAM_DDR3
        bool
 
@@ -476,6 +476,14 @@ config SUNXI_DRAM_H6_DDR3_1333
        This option is the DDR3 timing used by the boot0 on H6 TV boxes
        which use a DDR3-1333 timing.
 
+config SUNXI_DRAM_H616_DDR3_1333
+       bool "DDR3-1333 boot0 timings on the H616 DRAM controller"
+       select SUNXI_DRAM_DDR3
+       depends on DRAM_SUN50I_H616
+       help
+         This option is the DDR3 timing used by the boot0 on H616 TV boxes
+         which use a DDR3-1333 timing.
+
 config SUNXI_DRAM_DDR2_V3S
        bool "DDR2 found in V3s chip"
        select SUNXI_DRAM_DDR2
index 39a8756..4d78c04 100644 (file)
@@ -3,5 +3,4 @@ obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK)   += lpddr3_stock.o
 obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S)      += ddr2_v3s.o
 obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3)     += h6_lpddr3.o
 obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333)  += h6_ddr3_1333.o
-# currently only DDR3 is supported on H616
-obj-$(CONFIG_MACH_SUN50I_H616)         += h616_ddr3_1333.o
+obj-$(CONFIG_SUNXI_DRAM_H616_DDR3_1333)        += h616_ddr3_1333.o
index 4178ee6..f13735e 100644 (file)
@@ -7,6 +7,7 @@ CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
 CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e
 CONFIG_DRAM_SUN50I_H616_TPR10=0xf83438
 CONFIG_MACH_SUN50I_H616=y
+CONFIG_SUNXI_DRAM_H616_DDR3_1333=y
 CONFIG_R_I2C_ENABLE=y
 CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
index 32ef0a4..318951e 100644 (file)
@@ -10,6 +10,7 @@ CONFIG_DRAM_SUN50I_H616_TPR10=0x2f0007
 CONFIG_DRAM_SUN50I_H616_TPR11=0xffffdddd
 CONFIG_DRAM_SUN50I_H616_TPR12=0xfedf7557
 CONFIG_MACH_SUN50I_H616=y
+CONFIG_SUNXI_DRAM_H616_DDR3_1333=y
 CONFIG_R_I2C_ENABLE=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y