static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24);
static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25);
static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26);
+static MESON_GATE(g12a_efuse, HHI_GCLK_SP_MPEG, 1);
/* Array of all clocks provided by this provider */
[CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
[CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
[CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
+ [CLKID_EFUSE] = &g12a_efuse.hw,
[CLKID_CPU_FCLK_P] = &g12a_cpu_fclk_p.hw,
[CLKID_CPU_CLK] = &g12a_cpu_clk.mux.hw,
&g12a_vclk2_venclmmc,
&g12a_vclk2_vencl,
&g12a_vclk2_other1,
+ &g12a_efuse,
&g12a_24m,
&g12a_12m_gate,
};
#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
+#define HHI_GCLK_SP_MPEG 0x154 /* 0x55 offset in data sheet */
#define HHI_APICALGDC_CNTL 0x168 /* 0x5a offset in data sheet */
#define CLKID_VCLK2_VENCL (GATE_BASE3 + 17)
#define CLKID_VCLK2_OTHER1 (GATE_BASE3 + 18)
-#define GATE_AO_BASE (GATE_BASE3 + 19)
+/*HHI_GCLK_SP_MPEG: 0x55*/
+#define GATE_BASE4 (GATE_BASE3 + 19)
+#define CLKID_EFUSE (GATE_BASE4 + 0)
+
+#define GATE_AO_BASE (GATE_BASE4 + 1)
#define CLKID_AO_MEDIA_CPU (GATE_AO_BASE + 0)
#define CLKID_AO_AHB_SRAM (GATE_AO_BASE + 1)
#define CLKID_AO_AHB_BUS (GATE_AO_BASE + 2)