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[arm] Remove remaining references to arm feature sets
authorRichard Earnshaw <rearnsha@arm.com>
Thu, 15 Dec 2016 15:50:24 +0000 (15:50 +0000)
committerRichard Earnshaw <rearnsha@gcc.gnu.org>
Thu, 15 Dec 2016 15:50:24 +0000 (15:50 +0000)
Nothing uses the old feature sets now, so we can delete them entirely.

* arm-cores.def: Remove FLAGS field from all core definitions.
* arm-arches.def: Likewise.
* arm-opts.h (enum processor_type): Remove FLAGS parameter from
ARM_CORES macro.
(arm_arch_core_flags): Likewise, plus ARM_ARCH macro.
* arm-protos.h (FL_*): Delete.
(arm_feature_set): Delete.
(ARM_FSET_*): Delete.
* arm.c (struct processors): Delete flags field.
(all_cores): Delete FLAGS parameter from macro, don't initialize flags.
(all architectures): Likewise.

From-SVN: r243705

gcc/ChangeLog patch | blob | history
gcc/common/config/arm/arm-common.c patch | blob | history
gcc/config/arm/arm-arches.def patch | blob | history
gcc/config/arm/arm-cores.def patch | blob | history
gcc/config/arm/arm-flags.h patch | blob | history
gcc/config/arm/arm-opts.h patch | blob | history
gcc/config/arm/arm.c patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 95e5d1e..fddd26d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,19 @@
 2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
 
+       * arm-cores.def: Remove FLAGS field from all core definitions.
+       * arm-arches.def: Likewise.
+       * arm-opts.h (enum processor_type): Remove FLAGS parameter from
+       ARM_CORES macro.
+       (arm_arch_core_flags): Likewise, plus ARM_ARCH macro.
+       * arm-protos.h (FL_*): Delete.
+       (arm_feature_set): Delete.
+       (ARM_FSET_*): Delete.
+       * arm.c (struct processors): Delete flags field.
+       (all_cores): Delete FLAGS parameter from macro, don't initialize flags.
+       (all architectures): Likewise.
+
+2016-12-15  Richard Earnshaw  <rearnsha@arm.com>
+
        * arm-opts.h (struct arm_arch_core_flag): Add new field ISA.
        Initialize it.
        (arm_arch_core_flag): Delete flags field.
diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c
index dca3682..611675b 100644 (file)
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -107,12 +107,12 @@ struct arm_arch_core_flag
 static const struct arm_arch_core_flag arm_arch_core_flags[] =
 {
 #undef ARM_CORE
-#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS)  \
+#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, COSTS) \
   {NAME, {ISA isa_nobit}},
 #include "config/arm/arm-cores.def"
 #undef ARM_CORE
 #undef ARM_ARCH
-#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA, FLAGS)     \
+#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA)    \
   {NAME, {ISA isa_nobit}},
 #include "config/arm/arm-arches.def"
 #undef ARM_ARCH
diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index 02ece42..ed6b0b6 100644 (file)
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -19,50 +19,49 @@
 
 /* Before using #include to read this file, define a macro:
 
-      ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA, FLAGS)
+      ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA)
 
    The NAME is the name of the architecture, represented as a string
    constant.  The CORE is the identifier for a core representative of
    this architecture.  ARCH is the architecture revision.  ISA is the
    detailed architectural capabilities of the core (see arm-isa.h).
-   FLAGS is the set of feature flags implied by the architecture.
 
    genopt.sh assumes no whitespace up to the first "," in each entry.  */
 
-ARM_ARCH("armv2",   arm2,       (TF_CO_PROC | TF_NO_MODE32), 2,                ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
-ARM_ARCH("armv2a",  arm2,       (TF_CO_PROC | TF_NO_MODE32), 2,                ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
-ARM_ARCH("armv3",   arm6,       TF_CO_PROC,                 3,         ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3))
-ARM_ARCH("armv3m",  arm7m,      TF_CO_PROC,                 3M,        ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M))
-ARM_ARCH("armv4",   arm7tdmi,   TF_CO_PROC,                 4,         ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4))
-/* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
+ARM_ARCH("armv2",   arm2,      (TF_CO_PROC | TF_NO_MODE32), 2,         ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26))
+ARM_ARCH("armv2a",  arm2,      (TF_CO_PROC | TF_NO_MODE32), 2,         ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26))
+ARM_ARCH("armv3",   arm6,      TF_CO_PROC,                  3,         ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26))
+ARM_ARCH("armv3m",  arm7m,     TF_CO_PROC,                  3M,        ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26))
+ARM_ARCH("armv4",   arm7tdmi,  TF_CO_PROC,                  4,         ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26))
+/* Strictly, isa_bit_mode26 is a permitted option for v4t, but there are no
    implementations that support it, so we will leave it out for now.  */
-ARM_ARCH("armv4t",  arm7tdmi,   TF_CO_PROC,                 4T,        ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T))
-ARM_ARCH("armv5",   arm10tdmi,  TF_CO_PROC,                 5,         ISA_FEAT(ISA_ARMv5), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5))
-ARM_ARCH("armv5t",  arm10tdmi,  TF_CO_PROC,                 5T,        ISA_FEAT(ISA_ARMv5t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T))
-ARM_ARCH("armv5e",  arm1026ejs, TF_CO_PROC,                 5E,        ISA_FEAT(ISA_ARMv5e), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5E))
-ARM_ARCH("armv5te", arm1026ejs, TF_CO_PROC,                 5TE,       ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE))
-ARM_ARCH("armv6",   arm1136js,  TF_CO_PROC,                 6,         ISA_FEAT(ISA_ARMv6), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6))
-ARM_ARCH("armv6j",  arm1136js,  TF_CO_PROC,                 6J,        ISA_FEAT(ISA_ARMv6j), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J))
-ARM_ARCH("armv6k",  mpcore,    TF_CO_PROC,                  6K,        ISA_FEAT(ISA_ARMv6k), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K))
-ARM_ARCH("armv6z",  arm1176jzs, TF_CO_PROC,                 6Z,        ISA_FEAT(ISA_ARMv6z), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6Z))
-ARM_ARCH("armv6kz", arm1176jzs, TF_CO_PROC,                 6KZ,       ISA_FEAT(ISA_ARMv6kz), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
-ARM_ARCH("armv6zk", arm1176jzs, TF_CO_PROC,                 6KZ,       ISA_FEAT(ISA_ARMv6kz), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
-ARM_ARCH("armv6t2", arm1156t2s, TF_CO_PROC,                 6T2,       ISA_FEAT(ISA_ARMv6t2), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2))
-ARM_ARCH("armv6-m", cortexm1,  0,                           6M,        ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
-ARM_ARCH("armv6s-m", cortexm1, 0,                           6M,        ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
-ARM_ARCH("armv7",   cortexa8,  TF_CO_PROC,                  7,         ISA_FEAT(ISA_ARMv7), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7))
-ARM_ARCH("armv7-a", cortexa8,  TF_CO_PROC,                  7A,        ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A))
-ARM_ARCH("armv7ve", cortexa8,  TF_CO_PROC,                  7A,        ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7VE))
-ARM_ARCH("armv7-r", cortexr4,  TF_CO_PROC,                  7R,        ISA_FEAT(ISA_ARMv7r), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R))
-ARM_ARCH("armv7-m", cortexm3,  TF_CO_PROC,                  7M,        ISA_FEAT(ISA_ARMv7m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M))
-ARM_ARCH("armv7e-m", cortexm4,  TF_CO_PROC,                 7EM,       ISA_FEAT(ISA_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM))
-ARM_ARCH("armv8-a", cortexa53,  TF_CO_PROC,                 8A,        ISA_FEAT(ISA_ARMv8a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A))
-ARM_ARCH("armv8-a+crc",cortexa53, TF_CO_PROC,               8A,        ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32  | FL_FOR_ARCH8A))
-ARM_ARCH("armv8.1-a", cortexa53,  TF_CO_PROC,               8A,        ISA_FEAT(ISA_ARMv8_1a), ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A))
-ARM_ARCH ("armv8.2-a", cortexa53,  TF_CO_PROC,              8A,        ISA_FEAT(ISA_ARMv8_2a), ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A))
-ARM_ARCH ("armv8.2-a+fp16", cortexa53, TF_CO_PROC,          8A,        ISA_FEAT(ISA_ARMv8_2a) ISA_FEAT(isa_bit_fp16), ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A | FL2_FP16INST))
-ARM_ARCH("armv8-m.base", cortexm23, 0,                      8M_BASE,   ISA_FEAT(ISA_ARMv8m_base), ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE))
-ARM_ARCH("armv8-m.main", cortexm7, TF_CO_PROC,              8M_MAIN,   ISA_FEAT(ISA_ARMv8m_main), ARM_FSET_MAKE (FL_FOR_ARCH8M_MAIN, FL2_CMSE))
-ARM_ARCH("armv8-m.main+dsp", cortexm33, TF_CO_PROC,         8M_MAIN,   ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em), ARM_FSET_MAKE (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
-ARM_ARCH("iwmmxt",  iwmmxt, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
-ARM_ARCH("iwmmxt2", iwmmxt2, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE,        ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
+ARM_ARCH("armv4t",  arm7tdmi,  TF_CO_PROC,                  4T,        ISA_FEAT(ISA_ARMv4t))
+ARM_ARCH("armv5",   arm10tdmi, TF_CO_PROC,                  5,         ISA_FEAT(ISA_ARMv5))
+ARM_ARCH("armv5t",  arm10tdmi, TF_CO_PROC,                  5T,        ISA_FEAT(ISA_ARMv5t))
+ARM_ARCH("armv5e",  arm1026ejs, TF_CO_PROC,                 5E,        ISA_FEAT(ISA_ARMv5e))
+ARM_ARCH("armv5te", arm1026ejs, TF_CO_PROC,                 5TE,       ISA_FEAT(ISA_ARMv5te))
+ARM_ARCH("armv6",   arm1136js, TF_CO_PROC,                  6,         ISA_FEAT(ISA_ARMv6))
+ARM_ARCH("armv6j",  arm1136js, TF_CO_PROC,                  6J,        ISA_FEAT(ISA_ARMv6j))
+ARM_ARCH("armv6k",  mpcore,    TF_CO_PROC,                  6K,        ISA_FEAT(ISA_ARMv6k))
+ARM_ARCH("armv6z",  arm1176jzs, TF_CO_PROC,                 6Z,        ISA_FEAT(ISA_ARMv6z))
+ARM_ARCH("armv6kz", arm1176jzs, TF_CO_PROC,                 6KZ,       ISA_FEAT(ISA_ARMv6kz))
+ARM_ARCH("armv6zk", arm1176jzs, TF_CO_PROC,                 6KZ,       ISA_FEAT(ISA_ARMv6kz))
+ARM_ARCH("armv6t2", arm1156t2s, TF_CO_PROC,                 6T2,       ISA_FEAT(ISA_ARMv6t2))
+ARM_ARCH("armv6-m", cortexm1,  0,                           6M,        ISA_FEAT(ISA_ARMv6m))
+ARM_ARCH("armv6s-m", cortexm1, 0,                           6M,        ISA_FEAT(ISA_ARMv6m))
+ARM_ARCH("armv7",   cortexa8,  TF_CO_PROC,                  7,         ISA_FEAT(ISA_ARMv7))
+ARM_ARCH("armv7-a", cortexa8,  TF_CO_PROC,                  7A,        ISA_FEAT(ISA_ARMv7a))
+ARM_ARCH("armv7ve", cortexa8,  TF_CO_PROC,                  7A,        ISA_FEAT(ISA_ARMv7ve))
+ARM_ARCH("armv7-r", cortexr4,  TF_CO_PROC,                  7R,        ISA_FEAT(ISA_ARMv7r))
+ARM_ARCH("armv7-m", cortexm3,  TF_CO_PROC,                  7M,        ISA_FEAT(ISA_ARMv7m))
+ARM_ARCH("armv7e-m", cortexm4, TF_CO_PROC,                  7EM,       ISA_FEAT(ISA_ARMv7em))
+ARM_ARCH("armv8-a", cortexa53, TF_CO_PROC,                  8A,        ISA_FEAT(ISA_ARMv8a))
+ARM_ARCH("armv8-a+crc",cortexa53, TF_CO_PROC,               8A,        ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32))
+ARM_ARCH("armv8.1-a", cortexa53,  TF_CO_PROC,               8A,        ISA_FEAT(ISA_ARMv8_1a))
+ARM_ARCH ("armv8.2-a", cortexa53,  TF_CO_PROC,              8A,        ISA_FEAT(ISA_ARMv8_2a))
+ARM_ARCH ("armv8.2-a+fp16", cortexa53, TF_CO_PROC,          8A,        ISA_FEAT(ISA_ARMv8_2a) ISA_FEAT(isa_bit_fp16))
+ARM_ARCH("armv8-m.base", cortexm23, 0,                      8M_BASE,   ISA_FEAT(ISA_ARMv8m_base))
+ARM_ARCH("armv8-m.main", cortexm7, TF_CO_PROC,              8M_MAIN,   ISA_FEAT(ISA_ARMv8m_main))
+ARM_ARCH("armv8-m.main+dsp", cortexm33, TF_CO_PROC,         8M_MAIN,   ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em))
+ARM_ARCH("iwmmxt",  iwmmxt, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt))
+ARM_ARCH("iwmmxt2", iwmmxt2, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE,        ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2))
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 7f64a1f..a232d37 100644 (file)
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -25,7 +25,7 @@
 
 /* Before using #include to read this file, define a macro:
 
-      ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS)
+      ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, TUNE_FLAGS, ARCH, ISA, COSTS)
 
    The CORE_NAME is the name of the core, represented as a string constant.
    The INTERNAL_IDENT is the name of the core represented as an identifier.
@@ -35,8 +35,6 @@
    TUNE_FLAGS is a set of flag bits that are used to affect tuning.
    ARCH is the architecture revision implemented by the chip.
    ISA is the detailed architectural capabilities of the core (see arm-isa.h).
-   FLAGS is the set of feature flags of that core.
-   This need not include flags implied by the architecture.
    COSTS is the name of the rtx_costs routine to use.
 
    If you update this table, you must update the "tune" attribute in
@@ -45,146 +43,146 @@
    Some tools assume no whitespace up to the first "," in each entry.  */
 
 /* V2/V2A Architecture Processors */
-ARM_CORE("arm2",       arm2, arm2,             (TF_CO_PROC | TF_NO_MODE32),      2,    ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
-ARM_CORE("arm250",     arm250, arm250,         (TF_CO_PROC | TF_NO_MODE32),      2,    ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
-ARM_CORE("arm3",       arm3, arm3,             (TF_CO_PROC | TF_NO_MODE32),      2,    ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm2",       arm2, arm2,             (TF_CO_PROC | TF_NO_MODE32),      2,    ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm250",     arm250, arm250,         (TF_CO_PROC | TF_NO_MODE32),      2,    ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm3",       arm3, arm3,             (TF_CO_PROC | TF_NO_MODE32),      2,    ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), slowmul)
 
 /* V3 Architecture Processors */
-ARM_CORE("arm6",       arm6, arm6,             TF_CO_PROC,                       3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm60",      arm60, arm60,           TF_CO_PROC,                       3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm600",     arm600, arm600,         (TF_CO_PROC | TF_WBUF),           3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm610",     arm610, arm610,         TF_WBUF,                          3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm620",     arm620, arm620,         (TF_CO_PROC | TF_WBUF),           3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7",       arm7, arm7,             TF_CO_PROC,                       3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7d",      arm7d, arm7d,           TF_CO_PROC,                       3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7di",     arm7di, arm7di,         TF_CO_PROC,                       3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm70",      arm70, arm70,           TF_CO_PROC,                       3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm700",     arm700, arm700,         (TF_CO_PROC | TF_WBUF),           3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm700i",    arm700i, arm700i,       (TF_CO_PROC | TF_WBUF),           3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm710",     arm710, arm710,         TF_WBUF,                          3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm720",     arm720, arm720,         TF_WBUF,                          3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm710c",    arm710c, arm710c,       TF_WBUF,                          3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7100",    arm7100, arm7100,       TF_WBUF,                          3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7500",    arm7500, arm7500,       TF_WBUF,                          3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm6",       arm6, arm6,             TF_CO_PROC,                       3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm60",      arm60, arm60,           TF_CO_PROC,                       3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm600",     arm600, arm600,         (TF_CO_PROC | TF_WBUF),           3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm610",     arm610, arm610,         TF_WBUF,                          3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm620",     arm620, arm620,         (TF_CO_PROC | TF_WBUF),           3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm7",       arm7, arm7,             TF_CO_PROC,                       3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm7d",      arm7d, arm7d,           TF_CO_PROC,                       3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm7di",     arm7di, arm7di,         TF_CO_PROC,                       3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm70",      arm70, arm70,           TF_CO_PROC,                       3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm700",     arm700, arm700,         (TF_CO_PROC | TF_WBUF),           3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm700i",    arm700i, arm700i,       (TF_CO_PROC | TF_WBUF),           3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm710",     arm710, arm710,         TF_WBUF,                          3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm720",     arm720, arm720,         TF_WBUF,                          3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm710c",    arm710c, arm710c,       TF_WBUF,                          3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm7100",    arm7100, arm7100,       TF_WBUF,                          3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm7500",    arm7500, arm7500,       TF_WBUF,                          3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
 /* Doesn't have an external co-proc, but does have embedded fpa (fpa no-longer supported). */
-ARM_CORE("arm7500fe", arm7500fe, arm7500fe,    (TF_CO_PROC | TF_WBUF),           3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7500fe", arm7500fe, arm7500fe,    (TF_CO_PROC | TF_WBUF),           3,    ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
 
 /* V3M Architecture Processors */
 /* arm7m doesn't exist on its own, but only with D, ("and", and I), but
    those don't alter the code, so arm7m is sometimes used.  */
-ARM_CORE("arm7m",   arm7m, arm7m,              TF_CO_PROC,                       3M,   ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
-ARM_CORE("arm7dm",  arm7dm, arm7dm,            TF_CO_PROC,                       3M,   ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
-ARM_CORE("arm7dmi", arm7dmi, arm7dmi,          TF_CO_PROC,                       3M,   ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7m",   arm7m, arm7m,              TF_CO_PROC,                       3M,   ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), fastmul)
+ARM_CORE("arm7dm",  arm7dm, arm7dm,            TF_CO_PROC,                       3M,   ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), fastmul)
+ARM_CORE("arm7dmi", arm7dmi, arm7dmi,          TF_CO_PROC,                       3M,   ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), fastmul)
 
 /* V4 Architecture Processors */
-ARM_CORE("arm8",          arm8, arm8,                  TF_LDSCHED,               4,    ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul)
-ARM_CORE("arm810",        arm810, arm810,              TF_LDSCHED,               4,    ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul)
-ARM_CORE("strongarm",     strongarm, strongarm,                (TF_LDSCHED | TF_STRONG), 4,    ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm110",  strongarm110, strongarm110,  (TF_LDSCHED | TF_STRONG), 4,    ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm1100", strongarm1100, strongarm1100, (TF_LDSCHED | TF_STRONG), 4,   ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm1110", strongarm1110, strongarm1110, (TF_LDSCHED | TF_STRONG), 4,   ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("fa526",         fa526, fa526,                        TF_LDSCHED,               4,    ISA_FEAT(ISA_ARMv4), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul)
-ARM_CORE("fa626",         fa626, fa626,                        TF_LDSCHED,               4,    ISA_FEAT(ISA_ARMv4), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul)
+ARM_CORE("arm8",         arm8, arm8,                   TF_LDSCHED,               4,    ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), fastmul)
+ARM_CORE("arm810",       arm810, arm810,               TF_LDSCHED,               4,    ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), fastmul)
+ARM_CORE("strongarm",    strongarm, strongarm,         (TF_LDSCHED | TF_STRONG), 4,    ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
+ARM_CORE("strongarm110",  strongarm110, strongarm110,  (TF_LDSCHED | TF_STRONG), 4,    ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
+ARM_CORE("strongarm1100", strongarm1100, strongarm1100, (TF_LDSCHED | TF_STRONG), 4,   ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
+ARM_CORE("strongarm1110", strongarm1110, strongarm1110, (TF_LDSCHED | TF_STRONG), 4,   ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
+ARM_CORE("fa526",        fa526, fa526,                 TF_LDSCHED,               4,    ISA_FEAT(ISA_ARMv4), fastmul)
+ARM_CORE("fa626",        fa626, fa626,                 TF_LDSCHED,               4,    ISA_FEAT(ISA_ARMv4), fastmul)
 
 /* V4T Architecture Processors */
-ARM_CORE("arm7tdmi",   arm7tdmi, arm7tdmi,     TF_CO_PROC,                       4T,   ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm7tdmi-s", arm7tdmis, arm7tdmis,   TF_CO_PROC,                       4T,   ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm710t",    arm710t, arm710t,       TF_WBUF,                          4T,   ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm720t",    arm720t, arm720t,       TF_WBUF,                          4T,   ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm740t",    arm740t, arm740t,       TF_WBUF,                          4T,   ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm9",       arm9, arm9,             TF_LDSCHED,                       4T,   ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm9tdmi",   arm9tdmi, arm9tdmi,     TF_LDSCHED,                       4T,   ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm920",     arm920, arm920,         TF_LDSCHED,                       4T,   ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm920t",    arm920t, arm920t,       TF_LDSCHED,                       4T,   ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm922t",    arm922t, arm922t,       TF_LDSCHED,                       4T,   ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm940t",    arm940t, arm940t,       TF_LDSCHED,                       4T,   ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("ep9312",     ep9312, ep9312,         TF_LDSCHED,                       4T,   ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm7tdmi",   arm7tdmi, arm7tdmi,     TF_CO_PROC,                       4T,   ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm7tdmi-s", arm7tdmis, arm7tdmis,   TF_CO_PROC,                       4T,   ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm710t",    arm710t, arm710t,       TF_WBUF,                          4T,   ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm720t",    arm720t, arm720t,       TF_WBUF,                          4T,   ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm740t",    arm740t, arm740t,       TF_WBUF,                          4T,   ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm9",       arm9, arm9,             TF_LDSCHED,                       4T,   ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm9tdmi",   arm9tdmi, arm9tdmi,     TF_LDSCHED,                       4T,   ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm920",     arm920, arm920,         TF_LDSCHED,                       4T,   ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm920t",    arm920t, arm920t,       TF_LDSCHED,                       4T,   ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm922t",    arm922t, arm922t,       TF_LDSCHED,                       4T,   ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm940t",    arm940t, arm940t,       TF_LDSCHED,                       4T,   ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("ep9312",     ep9312, ep9312,         TF_LDSCHED,                       4T,   ISA_FEAT(ISA_ARMv4t), fastmul)
 
 /* V5T Architecture Processors */
-ARM_CORE("arm10tdmi",  arm10tdmi, arm10tdmi,   TF_LDSCHED,                       5T,   ISA_FEAT(ISA_ARMv5t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul)
-ARM_CORE("arm1020t",   arm1020t, arm1020t,     TF_LDSCHED,                       5T,   ISA_FEAT(ISA_ARMv5t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul)
+ARM_CORE("arm10tdmi",  arm10tdmi, arm10tdmi,   TF_LDSCHED,                       5T,   ISA_FEAT(ISA_ARMv5t), fastmul)
+ARM_CORE("arm1020t",   arm1020t, arm1020t,     TF_LDSCHED,                       5T,   ISA_FEAT(ISA_ARMv5t), fastmul)
 
 /* V5TE Architecture Processors */
-ARM_CORE("arm9e",      arm9e, arm9e,           TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm946e-s",  arm946es, arm946es,     TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm966e-s",  arm966es, arm966es,     TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm968e-s",  arm968es, arm968es,     TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm10e",     arm10e, arm10e,         TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("arm1020e",   arm1020e, arm1020e,     TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("arm1022e",   arm1022e, arm1022e,     TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("xscale",     xscale, xscale,         (TF_LDSCHED | TF_XSCALE),         5TE,  ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale), ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("iwmmxt",     iwmmxt, iwmmxt,         (TF_LDSCHED | TF_XSCALE),         5TE,  ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt), ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("iwmmxt2",    iwmmxt2, iwmmxt2,       (TF_LDSCHED | TF_XSCALE),         5TE,  ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2), ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("fa606te",    fa606te, fa606te,       TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fa626te",    fa626te, fa626te,       TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fmp626",     fmp626, fmp626,         TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fa726te",    fa726te, fa726te,       TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fa726te)
+ARM_CORE("arm9e",      arm9e, arm9e,           TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), 9e)
+ARM_CORE("arm946e-s",  arm946es, arm946es,     TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), 9e)
+ARM_CORE("arm966e-s",  arm966es, arm966es,     TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), 9e)
+ARM_CORE("arm968e-s",  arm968es, arm968es,     TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), 9e)
+ARM_CORE("arm10e",     arm10e, arm10e,         TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), fastmul)
+ARM_CORE("arm1020e",   arm1020e, arm1020e,     TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), fastmul)
+ARM_CORE("arm1022e",   arm1022e, arm1022e,     TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), fastmul)
+ARM_CORE("xscale",     xscale, xscale,         (TF_LDSCHED | TF_XSCALE),         5TE,  ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale), xscale)
+ARM_CORE("iwmmxt",     iwmmxt, iwmmxt,         (TF_LDSCHED | TF_XSCALE),         5TE,  ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt), xscale)
+ARM_CORE("iwmmxt2",    iwmmxt2, iwmmxt2,       (TF_LDSCHED | TF_XSCALE),         5TE,  ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2), xscale)
+ARM_CORE("fa606te",    fa606te, fa606te,       TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), 9e)
+ARM_CORE("fa626te",    fa626te, fa626te,       TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), 9e)
+ARM_CORE("fmp626",     fmp626, fmp626,         TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), 9e)
+ARM_CORE("fa726te",    fa726te, fa726te,       TF_LDSCHED,                       5TE,  ISA_FEAT(ISA_ARMv5te), fa726te)
 
 /* V5TEJ Architecture Processors */
-ARM_CORE("arm926ej-s", arm926ejs, arm926ejs,   TF_LDSCHED,                       5TEJ, ISA_FEAT(ISA_ARMv5tej), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e)
-ARM_CORE("arm1026ej-s",        arm1026ejs, arm1026ejs, TF_LDSCHED,                       5TEJ, ISA_FEAT(ISA_ARMv5tej), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e)
+ARM_CORE("arm926ej-s", arm926ejs, arm926ejs,   TF_LDSCHED,                       5TEJ, ISA_FEAT(ISA_ARMv5tej), 9e)
+ARM_CORE("arm1026ej-s",        arm1026ejs, arm1026ejs, TF_LDSCHED,                       5TEJ, ISA_FEAT(ISA_ARMv5tej), 9e)
 
 /* V6 Architecture Processors */
-ARM_CORE("arm1136j-s",         arm1136js, arm1136js,           TF_LDSCHED,       6J,   ISA_FEAT(ISA_ARMv6j), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J), 9e)
-ARM_CORE("arm1136jf-s",                arm1136jfs, arm1136jfs,         TF_LDSCHED,       6J,   ISA_FEAT(ISA_ARMv6j) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6J), 9e)
-ARM_CORE("arm1176jz-s",                arm1176jzs, arm1176jzs,         TF_LDSCHED,       6KZ,  ISA_FEAT(ISA_ARMv6kz), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ), 9e)
-ARM_CORE("arm1176jzf-s",       arm1176jzfs, arm1176jzfs,       TF_LDSCHED,       6KZ,  ISA_FEAT(ISA_ARMv6kz) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6KZ), 9e)
-ARM_CORE("mpcorenovfp",                mpcorenovfp, mpcorenovfp,       TF_LDSCHED,       6K,   ISA_FEAT(ISA_ARMv6k), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K), 9e)
-ARM_CORE("mpcore",             mpcore, mpcore,                 TF_LDSCHED,       6K,   ISA_FEAT(ISA_ARMv6k) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6K), 9e)
-ARM_CORE("arm1156t2-s",                arm1156t2s, arm1156t2s,         TF_LDSCHED,       6T2,  ISA_FEAT(ISA_ARMv6t2), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2), v6t2)
-ARM_CORE("arm1156t2f-s",       arm1156t2fs, arm1156t2fs,       TF_LDSCHED,       6T2,  ISA_FEAT(ISA_ARMv6t2) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6T2), v6t2)
+ARM_CORE("arm1136j-s",         arm1136js, arm1136js,           TF_LDSCHED,       6J,   ISA_FEAT(ISA_ARMv6j), 9e)
+ARM_CORE("arm1136jf-s",                arm1136jfs, arm1136jfs,         TF_LDSCHED,       6J,   ISA_FEAT(ISA_ARMv6j) ISA_FEAT(isa_bit_VFPv2), 9e)
+ARM_CORE("arm1176jz-s",                arm1176jzs, arm1176jzs,         TF_LDSCHED,       6KZ,  ISA_FEAT(ISA_ARMv6kz), 9e)
+ARM_CORE("arm1176jzf-s",       arm1176jzfs, arm1176jzfs,       TF_LDSCHED,       6KZ,  ISA_FEAT(ISA_ARMv6kz) ISA_FEAT(isa_bit_VFPv2), 9e)
+ARM_CORE("mpcorenovfp",                mpcorenovfp, mpcorenovfp,       TF_LDSCHED,       6K,   ISA_FEAT(ISA_ARMv6k), 9e)
+ARM_CORE("mpcore",             mpcore, mpcore,                 TF_LDSCHED,       6K,   ISA_FEAT(ISA_ARMv6k) ISA_FEAT(isa_bit_VFPv2), 9e)
+ARM_CORE("arm1156t2-s",                arm1156t2s, arm1156t2s,         TF_LDSCHED,       6T2,  ISA_FEAT(ISA_ARMv6t2), v6t2)
+ARM_CORE("arm1156t2f-s",       arm1156t2fs, arm1156t2fs,       TF_LDSCHED,       6T2,  ISA_FEAT(ISA_ARMv6t2) ISA_FEAT(isa_bit_VFPv2), v6t2)
 
 /* V6M Architecture Processors */
-ARM_CORE("cortex-m1",          cortexm1, cortexm1,             TF_LDSCHED,       6M,   ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0",          cortexm0, cortexm0,             TF_LDSCHED,       6M,   ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0plus",      cortexm0plus, cortexm0plus,     TF_LDSCHED,       6M,   ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m1",          cortexm1, cortexm1,             TF_LDSCHED,       6M,   ISA_FEAT(ISA_ARMv6m), v6m)
+ARM_CORE("cortex-m0",          cortexm0, cortexm0,             TF_LDSCHED,       6M,   ISA_FEAT(ISA_ARMv6m), v6m)
+ARM_CORE("cortex-m0plus",      cortexm0plus, cortexm0plus,     TF_LDSCHED,       6M,   ISA_FEAT(ISA_ARMv6m), v6m)
 
 /* V6M Architecture Processors for small-multiply implementations.  */
-ARM_CORE("cortex-m1.small-multiply",   cortexm1smallmultiply, cortexm1,        (TF_LDSCHED | TF_SMALLMUL),  6M,        ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0.small-multiply",   cortexm0smallmultiply, cortexm0,        (TF_LDSCHED | TF_SMALLMUL),  6M,        ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus, (TF_LDSCHED | TF_SMALLMUL), 6M,       ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m1.small-multiply",   cortexm1smallmultiply, cortexm1,        (TF_LDSCHED | TF_SMALLMUL),  6M,        ISA_FEAT(ISA_ARMv6m), v6m)
+ARM_CORE("cortex-m0.small-multiply",   cortexm0smallmultiply, cortexm0,        (TF_LDSCHED | TF_SMALLMUL),  6M,        ISA_FEAT(ISA_ARMv6m), v6m)
+ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus, (TF_LDSCHED | TF_SMALLMUL), 6M,       ISA_FEAT(ISA_ARMv6m), v6m)
 
 /* V7 Architecture Processors */
-ARM_CORE("generic-armv7-a",    genericv7a, genericv7a,         TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex)
-ARM_CORE("cortex-a5",          cortexa5, cortexa5,             TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a5)
-ARM_CORE("cortex-a7",          cortexa7, cortexa7,             TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7)
-ARM_CORE("cortex-a8",          cortexa8, cortexa8,             TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a8)
-ARM_CORE("cortex-a9",          cortexa9, cortexa9,             TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a9)
-ARM_CORE("cortex-a12",         cortexa12, cortexa17,           TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
-ARM_CORE("cortex-a15",         cortexa15, cortexa15,           TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
-ARM_CORE("cortex-a17",         cortexa17, cortexa17,           TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
-ARM_CORE("cortex-r4",          cortexr4, cortexr4,             TF_LDSCHED,       7R,   ISA_FEAT(ISA_ARMv7r), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r4f",         cortexr4f, cortexr4f,           TF_LDSCHED,       7R,   ISA_FEAT(ISA_ARMv7r), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r5",          cortexr5, cortexr5,             TF_LDSCHED,       7R,   ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r7",          cortexr7, cortexr7,             TF_LDSCHED,       7R,   ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r8",          cortexr8, cortexr7,             TF_LDSCHED,       7R,   ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-m7",          cortexm7, cortexm7,             TF_LDSCHED,       7EM,  ISA_FEAT(ISA_ARMv7em) ISA_FEAT(isa_quirk_no_volatile_ce), ARM_FSET_MAKE_CPU1 (FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7)
-ARM_CORE("cortex-m4",          cortexm4, cortexm4,             TF_LDSCHED,       7EM,  ISA_FEAT(ISA_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM), v7m)
-ARM_CORE("cortex-m3",          cortexm3, cortexm3,             TF_LDSCHED,       7M,   ISA_FEAT(ISA_ARMv7m) ISA_FEAT(isa_quirk_cm3_ldrd), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m)
-ARM_CORE("marvell-pj4",                marvell_pj4, marvell_pj4,       TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), marvell_pj4)
+ARM_CORE("generic-armv7-a",    genericv7a, genericv7a,         TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a), cortex)
+ARM_CORE("cortex-a5",          cortexa5, cortexa5,             TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a), cortex_a5)
+ARM_CORE("cortex-a7",          cortexa7, cortexa7,             TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), cortex_a7)
+ARM_CORE("cortex-a8",          cortexa8, cortexa8,             TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a), cortex_a8)
+ARM_CORE("cortex-a9",          cortexa9, cortexa9,             TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a), cortex_a9)
+ARM_CORE("cortex-a12",         cortexa12, cortexa17,           TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), cortex_a12)
+ARM_CORE("cortex-a15",         cortexa15, cortexa15,           TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7ve), cortex_a15)
+ARM_CORE("cortex-a17",         cortexa17, cortexa17,           TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7ve), cortex_a12)
+ARM_CORE("cortex-r4",          cortexr4, cortexr4,             TF_LDSCHED,       7R,   ISA_FEAT(ISA_ARMv7r), cortex)
+ARM_CORE("cortex-r4f",         cortexr4f, cortexr4f,           TF_LDSCHED,       7R,   ISA_FEAT(ISA_ARMv7r), cortex)
+ARM_CORE("cortex-r5",          cortexr5, cortexr5,             TF_LDSCHED,       7R,   ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), cortex)
+ARM_CORE("cortex-r7",          cortexr7, cortexr7,             TF_LDSCHED,       7R,   ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), cortex)
+ARM_CORE("cortex-r8",          cortexr8, cortexr7,             TF_LDSCHED,       7R,   ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), cortex)
+ARM_CORE("cortex-m7",          cortexm7, cortexm7,             TF_LDSCHED,       7EM,  ISA_FEAT(ISA_ARMv7em) ISA_FEAT(isa_quirk_no_volatile_ce), cortex_m7)
+ARM_CORE("cortex-m4",          cortexm4, cortexm4,             TF_LDSCHED,       7EM,  ISA_FEAT(ISA_ARMv7em), v7m)
+ARM_CORE("cortex-m3",          cortexm3, cortexm3,             TF_LDSCHED,       7M,   ISA_FEAT(ISA_ARMv7m) ISA_FEAT(isa_quirk_cm3_ldrd), v7m)
+ARM_CORE("marvell-pj4",                marvell_pj4, marvell_pj4,       TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7a), marvell_pj4)
 
 /* V7 big.LITTLE implementations */
-ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,  TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
-ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,  TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,  TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7ve), cortex_a15)
+ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,  TF_LDSCHED,       7A,   ISA_FEAT(ISA_ARMv7ve), cortex_a12)
 
 /* V8 A-profile Architecture Processors */
-ARM_CORE("cortex-a32", cortexa32, cortexa53,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
-ARM_CORE("cortex-a35", cortexa35, cortexa53,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
-ARM_CORE("cortex-a53", cortexa53, cortexa53,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
-ARM_CORE("cortex-a57", cortexa57, cortexa57,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a72", cortexa72, cortexa57,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a73", cortexa73, cortexa57,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
-ARM_CORE("exynos-m1",  exynosm1,  exynosm1,    TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), exynosm1)
-ARM_CORE("falkor",     falkor,    cortexa57,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
-ARM_CORE("qdf24xx",    qdf24xx,   cortexa57,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
-ARM_CORE("xgene1",      xgene1,    xgene1,      TF_LDSCHED,                      8A,   ISA_FEAT(ISA_ARMv8a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A),            xgene1)
+ARM_CORE("cortex-a32", cortexa32, cortexa53,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a35)
+ARM_CORE("cortex-a35", cortexa35, cortexa53,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a35)
+ARM_CORE("cortex-a53", cortexa53, cortexa53,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a53)
+ARM_CORE("cortex-a57", cortexa57, cortexa57,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
+ARM_CORE("cortex-a72", cortexa72, cortexa57,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
+ARM_CORE("cortex-a73", cortexa73, cortexa57,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a73)
+ARM_CORE("exynos-m1",  exynosm1,  exynosm1,    TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), exynosm1)
+ARM_CORE("falkor",     falkor,    cortexa57,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), qdf24xx)
+ARM_CORE("qdf24xx",    qdf24xx,   cortexa57,   TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), qdf24xx)
+ARM_CORE("xgene1",     xgene1,    xgene1,      TF_LDSCHED,                       8A,   ISA_FEAT(ISA_ARMv8a), xgene1)
 
 /* V8 A-profile big.LITTLE implementations */
-ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, TF_LDSCHED,     8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, TF_LDSCHED,     8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, TF_LDSCHED,     8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
-ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, TF_LDSCHED,     8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
+ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, TF_LDSCHED,     8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
+ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, TF_LDSCHED,     8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
+ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, TF_LDSCHED,     8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a73)
+ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, TF_LDSCHED,     8A,   ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a73)
 
 /* V8 M-profile implementations.  */
-ARM_CORE("cortex-m23", cortexm23, cortexm23,   TF_LDSCHED,                       8M_BASE, ISA_FEAT(ISA_ARMv8m_base), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8M_BASE), v6m)
-ARM_CORE("cortex-m33", cortexm33, cortexm33,   TF_LDSCHED,                       8M_MAIN, ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m)
+ARM_CORE("cortex-m23", cortexm23, cortexm23,   TF_LDSCHED,                       8M_BASE, ISA_FEAT(ISA_ARMv8m_base), v6m)
+ARM_CORE("cortex-m33", cortexm33, cortexm33,   TF_LDSCHED,                       8M_MAIN, ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em), v7m)
diff --git a/gcc/config/arm/arm-flags.h b/gcc/config/arm/arm-flags.h
index 6482c64..a0d99a8 100644 (file)
--- a/gcc/config/arm/arm-flags.h
+++ b/gcc/config/arm/arm-flags.h
@@ -32,189 +32,4 @@
 #define TF_XSCALE      (1U << 5)
 #define TF_NO_MODE32   (1U << 6)
 
-/* Flags used to identify the presence of processor capabilities.  */
-
-/* Bit values used to identify processor capabilities.  */
-#define FL_NONE              (0U)              /* No flags.  */
-#define FL_ANY       (0xffffffffU)     /* All flags.  */
-#define FL_CO_PROC    (1U << 0)                /* Has external co-processor bus.  */
-#define FL_ARCH3M     (1U << 1)                /* Extended multiply.  */
-#define FL_MODE26     (1U << 2)                /* 26-bit mode support.  */
-#define FL_MODE32     (1U << 3)                /* 32-bit mode support.  */
-#define FL_ARCH4      (1U << 4)                /* Architecture rel 4.  */
-#define FL_ARCH5      (1U << 5)                /* Architecture rel 5.  */
-#define FL_THUMB      (1U << 6)                /* Thumb aware.  */
-/* Spare             (1U << 7)  */
-/* Spare             (1U << 8)  */
-#define FL_ARCH5E     (1U << 9)                /* DSP extensions to v5.  */
-#define FL_XSCALE     (1U << 10)       /* XScale.  */
-/* Spare             (1U << 11) */
-#define FL_ARCH6      (1U << 12)       /* Architecture rel 6.  Adds
-                                          media instructions.  */
-#define FL_VFPV2      (1U << 13)       /* Vector Floating Point V2.  */
-/* Spare             (1U << 14) */
-#define FL_ARCH6K     (1U << 15)       /* Architecture rel 6 K extensions.  */
-#define FL_THUMB2     (1U << 16)       /* Thumb-2.  */
-#define FL_NOTM              (1U << 17)        /* Instructions not present in the 'M'
-                                          profile.  */
-#define FL_THUMB_DIV  (1U << 18)       /* Hardware divide (Thumb mode).  */
-#define FL_VFPV3      (1U << 19)       /* Vector Floating Point V3.  */
-#define FL_NEON       (1U << 20)       /* Neon instructions.  */
-#define FL_ARCH7EM    (1U << 21)       /* Instructions present in the ARMv7E-M
-                                          architecture.  */
-#define FL_ARCH7      (1U << 22)       /* Architecture 7.  */
-#define FL_ARM_DIV    (1U << 23)       /* Hardware divide (ARM mode).  */
-#define FL_ARCH8      (1U << 24)       /* Architecture 8.  */
-#define FL_CRC32      (1U << 25)       /* ARMv8 CRC32 instructions.  */
-/* Spare             (1U << 26) */
-#define FL_NO_VOLATILE_CE  (1U << 27)  /* No volatile memory in IT block.  */
-
-#define FL_IWMMXT     (1U << 29)       /* XScale v2 or "Intel Wireless MMX
-                                          technology".  */
-#define FL_IWMMXT2    (1U << 30)       /* "Intel Wireless MMX2
-                                           technology".  */
-#define FL_ARCH6KZ    (1U << 31)       /* ARMv6KZ architecture.  */
-
-#define FL2_ARCH8_1   (1U << 0)                /* Architecture 8.1.  */
-#define FL2_ARCH8_2   (1U << 1)                /* Architecture 8.2.  */
-#define FL2_FP16INST  (1U << 2)                /* FP16 Instructions for ARMv8.2 and
-                                          later.  */
-#define FL2_CMSE      (1U << 3)                /* ARMv8-M Security Extensions.  */
-
-/* Flags that only effect tuning, not available instructions.  */
-#define FL_TUNE                (FL_VFPV2)
-
-#define FL_FOR_ARCH2           FL_NOTM
-#define FL_FOR_ARCH3           (FL_FOR_ARCH2 | FL_MODE32)
-#define FL_FOR_ARCH3M          (FL_FOR_ARCH3 | FL_ARCH3M)
-#define FL_FOR_ARCH4           (FL_FOR_ARCH3M | FL_ARCH4)
-#define FL_FOR_ARCH4T          (FL_FOR_ARCH4 | FL_THUMB)
-#define FL_FOR_ARCH5           (FL_FOR_ARCH4 | FL_ARCH5)
-#define FL_FOR_ARCH5T          (FL_FOR_ARCH5 | FL_THUMB)
-#define FL_FOR_ARCH5E          (FL_FOR_ARCH5 | FL_ARCH5E)
-#define FL_FOR_ARCH5TE         (FL_FOR_ARCH5E | FL_THUMB)
-#define FL_FOR_ARCH5TEJ                FL_FOR_ARCH5TE
-#define FL_FOR_ARCH6           (FL_FOR_ARCH5TE | FL_ARCH6)
-#define FL_FOR_ARCH6J          FL_FOR_ARCH6
-#define FL_FOR_ARCH6K          (FL_FOR_ARCH6 | FL_ARCH6K)
-#define FL_FOR_ARCH6Z          FL_FOR_ARCH6
-#define FL_FOR_ARCH6ZK         FL_FOR_ARCH6K
-#define FL_FOR_ARCH6KZ         (FL_FOR_ARCH6K | FL_ARCH6KZ)
-#define FL_FOR_ARCH6T2         (FL_FOR_ARCH6 | FL_THUMB2)
-#define FL_FOR_ARCH6M          (FL_FOR_ARCH6 & ~FL_NOTM)
-#define FL_FOR_ARCH7           ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
-#define FL_FOR_ARCH7A          (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
-#define FL_FOR_ARCH7VE         (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
-#define FL_FOR_ARCH7R          (FL_FOR_ARCH7A | FL_THUMB_DIV)
-#define FL_FOR_ARCH7M          (FL_FOR_ARCH7 | FL_THUMB_DIV)
-#define FL_FOR_ARCH7EM         (FL_FOR_ARCH7M | FL_ARCH7EM)
-#define FL_FOR_ARCH8A          (FL_FOR_ARCH7VE | FL_ARCH8)
-#define FL2_FOR_ARCH8_1A       FL2_ARCH8_1
-#define FL2_FOR_ARCH8_2A       (FL2_FOR_ARCH8_1A | FL2_ARCH8_2)
-#define FL_FOR_ARCH8M_BASE     (FL_FOR_ARCH6M | FL_ARCH8 | FL_THUMB_DIV)
-#define FL_FOR_ARCH8M_MAIN     (FL_FOR_ARCH7M | FL_ARCH8)
-
-/* There are too many feature bits to fit in a single word so the set of cpu and
-   fpu capabilities is a structure.  A feature set is created and manipulated
-   with the ARM_FSET macros.  */
-
-typedef struct
-{
-  unsigned cpu[2];
-} arm_feature_set;
-
-
-/* Initialize a feature set.  */
-
-#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
-
-#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
-#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
-
-/* Accessors.  */
-
-#define ARM_FSET_CPU1(S) ((S).cpu[0])
-#define ARM_FSET_CPU2(S) ((S).cpu[1])
-
-/* Useful combinations.  */
-
-#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
-#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
-
-/* Tests for a specific CPU feature.  */
-
-#define ARM_FSET_HAS_CPU1(A, F)  \
-  (((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F)))
-#define ARM_FSET_HAS_CPU2(A, F)  \
-  (((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F)))
-#define ARM_FSET_HAS_CPU(A, F1, F2)                            \
-  (ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2)))
-
-/* Add a feature to a feature set.  */
-
-#define ARM_FSET_ADD_CPU1(DST, F)              \
-  do {                                         \
-    (DST).cpu[0] |= (F);                       \
-  } while (0)
-
-#define ARM_FSET_ADD_CPU2(DST, F)              \
-  do {                                         \
-    (DST).cpu[1] |= (F);                       \
-  } while (0)
-
-/* Remove a feature from a feature set.  */
-
-#define ARM_FSET_DEL_CPU1(DST, F)              \
-  do {                                         \
-    (DST).cpu[0] &= ~(F);                      \
-  } while (0)
-
-#define ARM_FSET_DEL_CPU2(DST, F)              \
-  do {                                         \
-    (DST).cpu[1] &= ~(F);                      \
-  } while (0)
-
-/* Union of feature sets.  */
-
-#define ARM_FSET_UNION(DST,F1,F2)              \
-  do {                                         \
-    (DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0];  \
-    (DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1];  \
-  } while (0)
-
-/* Intersection of feature sets.  */
-
-#define ARM_FSET_INTER(DST,F1,F2)              \
-  do {                                         \
-    (DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0];  \
-    (DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1];  \
-  } while (0)
-
-/* Exclusive disjunction.  */
-
-#define ARM_FSET_XOR(DST,F1,F2)                                \
-  do {                                                 \
-    (DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0];          \
-    (DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1];          \
-  } while (0)
-
-/* Difference of feature sets: F1 excluding the elements of F2.  */
-
-#define ARM_FSET_EXCLUDE(DST,F1,F2)            \
-  do {                                         \
-    (DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0]; \
-    (DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1]; \
-  } while (0)
-
-/* Test for an empty feature set.  */
-
-#define ARM_FSET_IS_EMPTY(A)           \
-  (!((A).cpu[0]) && !((A).cpu[1]))
-
-/* Tests whether the cpu features of A are a subset of B.  */
-
-#define ARM_FSET_CPU_SUBSET(A,B)                                       \
-  ((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0])                           \
-   && (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
-
 #endif /* GCC_ARM_FLAGS_H */
diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h
index 52c69e9..3de110e 100644 (file)
--- a/gcc/config/arm/arm-opts.h
+++ b/gcc/config/arm/arm-opts.h
@@ -32,7 +32,7 @@
 enum processor_type
 {
 #undef ARM_CORE
-#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS) \
+#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, TUNE_FLAGS, ARCH, ISA, COSTS) \
   TARGET_CPU_##INTERNAL_IDENT,
 #include "arm-cores.def"
 #undef ARM_CORE
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 0b82714..822ef14 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -957,7 +957,6 @@ struct processors
   const char *arch;
   enum base_architecture base_arch;
   enum isa_feature isa_bits[isa_num_bits];
-  const arm_feature_set flags;
   const struct tune_params *const tune;
 };
 
@@ -2292,13 +2291,12 @@ const struct tune_params arm_fa726te_tune =
 static const struct processors all_cores[] =
 {
   /* ARM Cores */
-#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS)  \
+#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, COSTS) \
   {NAME, TARGET_CPU_##IDENT, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, \
-   {ISA isa_nobit}, FLAGS, &arm_##COSTS##_tune},
+   {ISA isa_nobit}, &arm_##COSTS##_tune},
 #include "arm-cores.def"
 #undef ARM_CORE
-  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit},
-   ARM_FSET_EMPTY, NULL}
+  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL}
 };
 
 static const struct processors all_architectures[] =
@@ -2307,12 +2305,12 @@ static const struct processors all_architectures[] =
   /* We don't specify tuning costs here as it will be figured out
      from the core.  */
 
-#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA, FLAGS)             \
+#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA)                    \
   {NAME, TARGET_CPU_##CORE, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH,       \
-  {ISA isa_nobit}, FLAGS, NULL},
+  {ISA isa_nobit}, NULL},
 #include "arm-arches.def"
 #undef ARM_ARCH
-  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, ARM_FSET_EMPTY, NULL}
+  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL}
 };
 
 /* The name of the preprocessor macro to define for this architecture.  PROFILE
Domain: System / Toolchain;