case Match_UImm20_0:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 20-bit unsigned immediate");
+ case Match_UImm26_0:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected 26-bit unsigned immediate");
}
llvm_unreachable("Implement any new match types added!");
//
class FJAL16_ins<bits<1> _X, string asmstr,
InstrItinClass itin>:
- FJAL16<_X, (outs), (ins simm20:$imm),
+ FJAL16<_X, (outs), (ins uimm26:$imm),
!strconcat(asmstr, "\t$imm\n\tnop"),[],
itin> {
let isCodeGenOnly=1;
class FJALB16_ins<bits<1> _X, string asmstr,
InstrItinClass itin>:
- FJAL16<_X, (outs), (ins simm20:$imm),
+ FJAL16<_X, (outs), (ins uimm26:$imm),
!strconcat(asmstr, "\t$imm\t# branch\n\tnop"),[],
itin> {
let isCodeGenOnly=1;
// uimm5 < uimm5_64, and uimm5 < vsplat_uimm5
// This is entirely arbitrary. We need an ordering and what we pick is
// unimportant since only one is possible for a given mnemonic.
+def ConstantUImm26AsmOperandClass
+ : ConstantUImmAsmOperandClass<26, []>;
def ConstantUImm20AsmOperandClass
- : ConstantUImmAsmOperandClass<20, []>;
+ : ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>;
def UImm16RelaxedAsmOperandClass
: UImmAsmOperandClass<16, [ConstantUImm20AsmOperandClass]> {
let Name = "UImm16_Relaxed";
let ParserMatchClass = MipsJumpTargetAsmOperand;
}
-def simm20 : Operand<i32>;
def simm32 : Operand<i32>;
def simm16_64 : Operand<i64> {
}
// Unsigned Operands
-foreach I = {1, 2, 3, 4, 5, 6, 7, 8, 10, 20} in
+foreach I = {1, 2, 3, 4, 5, 6, 7, 8, 10, 20, 26} in
def uimm # I : Operand<i32> {
let PrintMethod = "printUImm<" # I # ">";
let ParserMatchClass =