drm/vc4: dsi: Correct max divider to 255 (not 7)

The integer divider from parent PLL to DSI clock is capable
of going up to /255, not just /7 that the driver was trying.
This allows for slower link frequencies on the DSI bus where
the resolution permits.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>

diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c
index 9e349ba..cf924bf 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_dsi.c
+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
@@ -850,7 +850,7 @@ static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
        /* Find what divider gets us a faster clock than the requested
         * pixel clock.
         */
-       for (divider = 1; divider < 7; divider++) {
+       for (divider = 1; divider < 255; divider++) {
                if (parent_rate / (divider + 1) < pll_clock)
                        break;
        }