riscv: switch has_fpu() to the unified static key mechanism
authorJisheng Zhang <jszhang@kernel.org>
Sun, 22 May 2022 15:35:43 +0000 (23:35 +0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 16 Jun 2022 17:51:31 +0000 (10:51 -0700)
This is to use the unified static key mechanism instead of putting
static key related here and there.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20220522153543.2656-3-jszhang@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/switch_to.h
arch/riscv/kernel/cpufeature.c

index 0a3f4f9..1146348 100644 (file)
@@ -8,6 +8,7 @@
 
 #include <linux/jump_label.h>
 #include <linux/sched/task_stack.h>
+#include <asm/hwcap.h>
 #include <asm/processor.h>
 #include <asm/ptrace.h>
 #include <asm/csr.h>
@@ -56,10 +57,9 @@ static inline void __switch_to_aux(struct task_struct *prev,
        fstate_restore(next, task_pt_regs(next));
 }
 
-extern struct static_key_false cpu_hwcap_fpu;
 static __always_inline bool has_fpu(void)
 {
-       return static_branch_likely(&cpu_hwcap_fpu);
+       return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_FPU]);
 }
 #else
 static __always_inline bool has_fpu(void) { return false; }
index 62843a3..4fbfa1b 100644 (file)
@@ -27,9 +27,6 @@ unsigned long elf_hwcap __read_mostly;
 /* Host ISA bitmap */
 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
 
-#ifdef CONFIG_FPU
-__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu);
-#endif
 __ro_after_init DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX);
 EXPORT_SYMBOL(riscv_isa_ext_keys);
 
@@ -245,10 +242,6 @@ void __init riscv_fill_hwcap(void)
                if (j >= 0)
                        static_branch_enable(&riscv_isa_ext_keys[j]);
        }
-#ifdef CONFIG_FPU
-       if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
-               static_branch_enable(&cpu_hwcap_fpu);
-#endif
 }
 
 #ifdef CONFIG_RISCV_ALTERNATIVE