net: ax88796c_spi: support old miiphy.h definitions

This patch supports old style miiphy.h definitions because the
ax88796c_spi driver only supports old version u-boot. To match
the code style, just copied the definitions from previous u-boot.

Change-Id: I6c1b108a229f5aed7de031cdb31d341192c5cad6
Signed-off-by: Jaeyong Lee <jaeyong2.lee@samsung.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>

diff --git a/drivers/net/ax88796c_spi.h b/drivers/net/ax88796c_spi.h
index 3f0d165f1825b6df2046ac5f275ae91728bddf35..44a2f78256a0a39721c023225fbe6e87ff98aeb4 100644 (file)
--- a/drivers/net/ax88796c_spi.h
+++ b/drivers/net/ax88796c_spi.h
@@ -451,4 +451,72 @@ struct rx_header {
 #define P7_WFPC0       (0xFA)
 #define P7_WFPC1       (0xFC)
 
+/* Copied from old u-boot */
+#define PHY_BMCR               0x00
+#define PHY_BMSR               0x01
+#define PHY_PHYIDR1            0x02
+#define PHY_PHYIDR2            0x03
+#define PHY_ANAR               0x04
+#define PHY_ANLPAR             0x05
+#define PHY_ANER               0x06
+#define PHY_ANNPTR             0x07
+#define PHY_ANLPNP             0x08
+#define PHY_1000BTCR   0x09
+#define PHY_1000BTSR   0x0A
+#define PHY_EXSR               0x0F
+#define PHY_PHYSTS             0x10
+#define PHY_MIPSCR             0x11
+#define PHY_MIPGSR             0x12
+#define PHY_DCR                        0x13
+#define PHY_FCSCR              0x14
+#define PHY_RECR               0x15
+#define PHY_PCSR               0x16
+#define PHY_LBR                        0x17
+#define PHY_10BTSCR            0x18
+#define PHY_PHYCTRL            0x19
+
+/* PHY BMCR */
+#define PHY_BMCR_RESET         0x8000
+#define PHY_BMCR_LOOP          0x4000
+#define PHY_BMCR_100MB         0x2000
+#define PHY_BMCR_AUTON         0x1000
+#define PHY_BMCR_POWD          0x0800
+#define PHY_BMCR_ISO           0x0400
+#define PHY_BMCR_RST_NEG       0x0200
+#define PHY_BMCR_DPLX          0x0100
+#define PHY_BMCR_COL_TST       0x0080
+
+#define PHY_BMCR_SPEED_MASK    0x2040
+#define PHY_BMCR_1000_MBPS     0x0040
+#define PHY_BMCR_100_MBPS      0x2000
+#define PHY_BMCR_10_MBPS       0x0000
+
+/* phy BMSR */
+#define PHY_BMSR_100T4         0x8000
+#define PHY_BMSR_100TXF                0x4000
+#define PHY_BMSR_100TXH                0x2000
+#define PHY_BMSR_10TF          0x1000
+#define PHY_BMSR_10TH          0x0800
+#define PHY_BMSR_EXT_STAT      0x0100
+#define PHY_BMSR_PRE_SUP       0x0040
+#define PHY_BMSR_AUTN_COMP     0x0020
+#define PHY_BMSR_RF                    0x0010
+#define PHY_BMSR_AUTN_ABLE     0x0008
+#define PHY_BMSR_LS                    0x0004
+#define PHY_BMSR_JD                    0x0002
+#define PHY_BMSR_EXT           0x0001
+
+/*phy ANLPAR */
+#define PHY_ANLPAR_NP          0x8000
+#define PHY_ANLPAR_ACK         0x4000
+#define PHY_ANLPAR_RF          0x2000
+#define PHY_ANLPAR_ASYMP       0x0800
+#define PHY_ANLPAR_PAUSE       0x0400
+#define PHY_ANLPAR_T4          0x0200
+#define PHY_ANLPAR_TXFD                0x0100
+#define PHY_ANLPAR_TX          0x0080
+#define PHY_ANLPAR_10FD                0x0040
+#define PHY_ANLPAR_10          0x0020
+#define PHY_ANLPAR_100         0x0380  /* we can run at 100 */
+
 #endif /*end of CONFIG_DRIVER_AX88796C_SPI*/